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Design Automation for Embedded Systems

, Volume 22, Issue 1–2, pp 141–181 | Cite as

DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems

  • Georgia Giannopoulou
  • Peter Poplavko
  • Dario Socci
  • Pengcheng Huang
  • Nikolay Stoimenov
  • Paraskevas Bourgos
  • Lothar Thiele
  • Marius Bozga
  • Saddek Bensalem
  • Sylvain Girbal
  • Madeleine Faugere
  • Romain Soulat
  • Benoît Dupont de Dinechin
Article
  • 86 Downloads

Abstract

Mixed-criticality systems are promoted in industry due to their potential to reduce size, weight, power, and cost. Nonetheless, deploying mixed-criticality applications on commercial multi-core platforms remains a highly challenging problem. To name a few reasons: (i) Industrial mixed-criticality applications are usually complex reactive applications, which cannot be specified by traditional, e.g., dataflow-based, models of computation. Appropriate mixed-criticality models of computation built upon Vestal’s assumptions are missing; (ii) Scheduling such applications on multicores with shared resources, such as memory buses, requires that any timing interference among applications of different criticality is bounded in order to guarantee—the necessary for certification—temporal isolation and to enable incremental design; (iii) The implementation of isolation-preserving mixed-criticality schedulers is itself subject to certification. Hence, it needs to be not only efficient, but also provably correct. This paper proposes, for the first time, a complete design flow covering all aspects from specification, using a novel mixed-criticality aware model of computation (DOL-Critical), to correct-by-construction implementation, using the principle ‘what you verify is what you generate’ which is based on a novel variant of task automata. We demonstrate the applicability of our design flow with an industrial avionic test case on the state-of-the-art Kalray MPPA®-256.

Keywords

Real-time systems Mixed-criticality systems Multi-core scheduling Rigorous design Software synthesis Avionics 

Notes

Acknowledgements

The research leading to these results has received funding from the European Union Seventh Framework Programme (FP7/2007-2013) under grant agreement number 288175 (CERTAINTY project).

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  • Georgia Giannopoulou
    • 1
  • Peter Poplavko
    • 5
  • Dario Socci
    • 5
  • Pengcheng Huang
    • 1
  • Nikolay Stoimenov
    • 1
  • Paraskevas Bourgos
    • 6
  • Lothar Thiele
    • 1
  • Marius Bozga
    • 2
  • Saddek Bensalem
    • 2
  • Sylvain Girbal
    • 3
  • Madeleine Faugere
    • 3
  • Romain Soulat
    • 3
  • Benoît Dupont de Dinechin
    • 4
  1. 1.Computer Engineering and Communication Networks LaboratoryETH ZurichZurichSwitzerland
  2. 2.CNRS, VERIMAGUniv. Grenoble-AlpesGrenobleFrance
  3. 3.THALES Research and TechnologyPalaiseau CedexFrance
  4. 4.Kalray S.A.Montbonnot Saint MartinFrance
  5. 5.Mentor, A Siemens BusinessMontbonnotFrance
  6. 6.WINGS ICT Solutions PCAthensGreece

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