Design Automation for Embedded Systems

, Volume 20, Issue 3, pp 191–210 | Cite as

MFLP: a low power encoding for on chip networks

Article

Abstract

Network on chip (NoC) has been proposed as an appropriate solution for today’s on-chip communication challenges. Power dissipation has become a key factor in the NoCs because of their shrinking sizes. In this paper, we propose a new encoding approach aimed at power reduction by decreasing the number of switching activities on the buses. This approach assigns the symbols to data word in such a way that the more frequent words are sent by less power consumption. This algorithm dedicates the symbols with less ones to high probability data and uses transition signaling to transmit data. The proposed method, unlike the existing low power encoding, does not rely on spatial redundancy and keeps the width of the bus constant. Experimental evaluations show that our approach reduces the power dissipation up to 46 % with 2.70, 0.51, and 15.43 % power, critical path and area overhead in the NoCs, respectively.

Keywords

Low power encoding Network on Chip Switching activity  Power consumption Data compression 

References

  1. 1.
    Marculescu R et al (2009) Outstanding research problems in NoC domain: system, microarchitecture, and circuit perspectives. IEEE Trans Comput-Aided Des Integr Circuits Syst 28(1):3–21CrossRefGoogle Scholar
  2. 2.
    Benini L, De Micheli G (2002) Networks on chip: a new SoC paradigm. IEEE Comput 35(1):70–78CrossRefGoogle Scholar
  3. 3.
    Palma JCS, Indrusiak LS, Moraes FG, Ortiz AG, Glesner M, Reis RAL (2007) Inserting data encoding techniques into NoC-based systems. In: Proceedings of ISVLSI. pp 299–304Google Scholar
  4. 4.
    Pasricha S, Dutt N (2008) Trends in emerging on-chip interconnect technologies. IPSJ Trans Syst LSI Des Methodol 1:2–17CrossRefGoogle Scholar
  5. 5.
    Postman J, Krishna T, Edmonds C, Peh L, Chiang P (2013) SWIFT: A low-power network-on-chip implementing the token flow control router architecture with swing-reduced interconnects. IEEE Trans VLSI 21(8):1432–1446CrossRefGoogle Scholar
  6. 6.
    Reehal G, Ismail M (2014) A systematic design methodology for low-power NoCs. IEEE Trans VLSI 22(12):2585–2595CrossRefGoogle Scholar
  7. 7.
    Kulkarni M, Agrawal V (2011) Energy source lifetime optimization for a digital system through power management. In: 43rd Southeastern symposium on system theory, pp 73–78Google Scholar
  8. 8.
    Svensson C (2001) Optimum voltage swing on on-chip and off-chip interconnect. IEEE J Solid-State Circuits 36(7):1108–1112CrossRefGoogle Scholar
  9. 9.
    Wei L, Chen Z, Johnson M, Roy K, De V (1999) Design and optimization of dual-threshold circuits for low voltage low power applications. IEEE Trans VLSI 7(1):6–24CrossRefGoogle Scholar
  10. 10.
    Shin D, Kim W, Kwon S, Han TH (2011) Communication-aware VFI partitioning for GALS-based networks-on-chip. Des Autom Embed Syst 15(2):89–109CrossRefGoogle Scholar
  11. 11.
    Moyer B (2001) Low power design for embedded processors. Proc IEEE 89(11):1576–1587CrossRefGoogle Scholar
  12. 12.
    Snowdon DC, Ruocco S, Heiser G (2005) Power management and dynamic voltage scaling: Myths and facts. In: Proceedings of the workshop on power aware real-time computing, pp 1–7Google Scholar
  13. 13.
    Benini L, Bogliolo A, De Micheli G (2000) A survey of design techniques for system level dynamic power management. IEEE Trans VLSI 8(3):299–316CrossRefGoogle Scholar
  14. 14.
    Arelakis A, Stenstrom P (2014) SC2: a statistical compression cache scheme. In: Proceedings of the 41st annual international symposium on computer architectureGoogle Scholar
  15. 15.
    Anagnostopoulos I, Bartzas A, Filippopoulos I, Soudris D (2012) High-level customization framework for application-specific NoC architectures. Des Autom Embed Syst 16(4):339–361CrossRefGoogle Scholar
  16. 16.
    Palesi M, Ascia G, Fazzino F, Catania V (2011) Data encoding schemes in network on chip. IEEE Trans Comput-Aided Des Integr Circuits Syst 30(5):774–786CrossRefGoogle Scholar
  17. 17.
    Stan MR, Burleson WR (1994) Limited-weight codes for low power I/O. In: International workshop on low power design, pp 209–214Google Scholar
  18. 18.
    Stan MR, Burleson WP (1995) Bus-Invert coding for low- power I/O. IEEE Trans VLSI 3:49–59CrossRefGoogle Scholar
  19. 19.
    Kim KW, Baek KH, Shanbhag N, Liu CL, Kang S (2000) Coupling driven signal encoding scheme for low power interface design. In: Proceedings of ICCAD, pp 318–321Google Scholar
  20. 20.
    Benini L, De Micheli G, Macii E, Poncino M, Quer S (1997) System level power optimization of special purpose applications: the Beach solution. In: Proceedings of international symposium on low power electronics and design, Monterey, pp 24–29Google Scholar
  21. 21.
    Taassori M, Hessabi S (2009) Low power encoding in NOCs based on coupling transition avoidance. In: Proceedings of DSD conferences, pp 247–254Google Scholar
  22. 22.
    Mamidipaka MN, Hirschberg DS, Dutt ND (2003) Adaptive low power address encoding techniques using self-organizing lists. IEEE Trans VLSI 11(5):827–834CrossRefGoogle Scholar
  23. 23.
    Cheng WC, Pedram M (2002) Power-optimal encoding for a DRAM address bus. IEEE Trans VLSI 10(2):109–118CrossRefGoogle Scholar
  24. 24.
    Lee K, Lee SJ (2004) SILENT: serialized low energy transmission coding for on-chip interconnection networks. In: ICCAD, pp 448–451Google Scholar
  25. 25.
    Benini L, Macii A, Macii E, Poncino M, Scarsi R (2000) Architectures and synthesis algorithms for power-efficient bus interfaces. IEEE Trans Comput-Aided Des Integr Circuits Syst 19(9):969–980CrossRefGoogle Scholar
  26. 26.
    Lv T, Henkel J, Lekates H, Wolf W (2003) A dictionary based en/decoder scheme for low power data buses. IEEE Trans VLSI 11(5):943–951CrossRefGoogle Scholar
  27. 27.
    Brahmbhatt AR, Zhang J, Wu Q, Qiu Q (2006) Low power bus encoding using adaptive hybrid algorithm. In: Design Automation Conference (DAC), pp 987–990Google Scholar
  28. 28.
    Benini L, De Micheli G (2006) Networks on chips: technology and tools. murgan kufmann publishers, BurlingtonCrossRefGoogle Scholar
  29. 29.
    Jafarzadeh N, Palesi M, Khademzadeh A, Afzali-Kusha A (2014) Data encoding techniques for reducing energy consumption in network-on-chip. IEEE Trans VLSI 22(3):675–685CrossRefGoogle Scholar
  30. 30.
    Jafarzadeh N, Palesi M, Eskandari S, Hessabi S, Afzali-Kusha A (2015) Low energy yet reliable data communication scheme for network on chip. IEEE Trans Comput-Aided Des Integr Circuits Syst. 34(12):1892–1904CrossRefGoogle Scholar
  31. 31.
    Vitkovski R, Haukilahti A, Jantsch, Nilsson E (2004) Low-power and error coding for network-on-chip traffic. In: Proceedings of norchip, pp 20–23Google Scholar
  32. 32.
    Hale KC, Grot B, Keckler SW (2009) Segment gating for static energy reduction in networks-on-chip. In: Proceedings of network on chip architectures, pp 57–62Google Scholar
  33. 33.
    Raghunathant V, Srivastavat MB, Guptai RK (2003) A survey of techniques for energy efficient on-chip communication. In: Proceedings of design automation conference, pp 900–905Google Scholar
  34. 34.
    International Technology Roadmap for Semiconductors (ITRS), (2011) Available: http://www.itrs.net

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  1. 1.Department of Electrical and Electronic EngineeringEastern Mediterranean UniversityFamagustaTurkey
  2. 2.Department of Computer EngineeringSharif University of TechnologyTehranIran

Personalised recommendations