Design Automation for Embedded Systems

, Volume 19, Issue 3, pp 301–326 | Cite as

FoRTReSS: a flow for design space exploration of partially reconfigurable systems

  • François Duhem
  • Fabrice Muller
  • Robin Bonamy
  • Sébastien Bilavarn
Article

Abstract

In this paper, we present a flow enabling design space exploration for partially reconfigurable systems with real-time constraints, called FoRTReSS. FoRTReSS allows estimating mixed hardware/software implementations of an application where the hardware design space, the floorplanning of reconfigurable regions placed on the FPGA, is automatically inferred from application resources information, interface constraints and the target device. Real-time constraints are verified by a highly configurable SystemC simulator, RecoSim, handling applications described as control data flow graphs (CDFGs). We demonstrate our approach on an H.264 video decoder and an H.265 encoder targeting the latest Zynq-7000 platforms from Xilinx, embedding a Cortex-A9 dual-core processor. We show that an hardware/software implementation of the H.264 decoder using both processor cores and slice decomposition is possible under real-time constraints, effectively achieving a framerate of 30 frames per second while reducing area requirements compared to a static implementation, using 54 % less slice resources and 44 % less BRAM resources. Additionally we report the ability of the methodology to address very early analysis from high level application specification on the example of an H.265 encoder.

Keywords

Reconfigurable architecture Design space exploration  Real-time systems Partial reconfiguration Field programmable gate arrays 

Notes

Acknowledgments

This work was carried out in the framework of project ARDMAHN [37] sponsored by the French National Research Agency under grant ANR-09-SEGI-001, which aims at developing methodologies for home gateways integrating dynamic and partial reconfiguration. This work is also carried out under the BENEFIC project (CA505), a project labelled within the framework of CATRENE, the EUREKA cluster for Application and Technology Research in Europe on NanoElectronics.

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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • François Duhem
    • 1
  • Fabrice Muller
    • 1
  • Robin Bonamy
    • 1
  • Sébastien Bilavarn
    • 1
  1. 1.University of Nice-Sophia Antipolis - CNRS/LEATSophia Antipolis CedexFrance

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