Design Automation for Embedded Systems

, Volume 17, Issue 3–4, pp 739–769 | Cite as

Self-aware Memory: an adaptive memory management system for upcoming manycore architectures and its decentralized self-optimization process

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Abstract

The number of cores per processor has been increased on and on in recent years. Carrying on with that, manycore processor systems will be the future system structure, and even within range for usage in desktop or mobile systems. But today’s manycore processors are primarily designed for high performance applications. Access to the external memory from the individual cores is avoided. As yet the system memory commonly consists of only one or a few memory components and offers access over a small number of controllers. This leads to congestion, inefficient memory assignment and the scalability of the memory is limited. However, there will be additional new scenarios, with multiple concurrently running dynamic applications, changing I/O characteristics and a not predictable memory usage in the near future. Highly dynamic workloads with varying memory usage have to be utilized. Consequently, the memory management must become more flexible and distributed in nature. Moreover, dynamic memory allocation will be a necessity, and a transparent optimization of the physical memory resource utilization can be done with integrated self-organization mechanisms, e.g. for locality, load distribution or energy efficiency issues. The autonomous self-optimizing memory architecture Self-aware Memory satisfies all these challenges with a scalable pooling of fully-decentralized interacting memory components. With it, flexible, reliable and scalable memory management is available. Access to private and shared memory is enabled in a flexible way and efficient synchronization mechanism are offered while contemporaneously providing comfortable usage and supporting well-known programming mechanisms. The presented evaluation addresses the parameters of the included self-optimization mechanism and their impact on the optimization. The results show that the overhead of the decentralized optimization process is amortized by the optimized runtime using the appropriate parameter settings.

Keywords

Optimization Adaptation Memory management  Self-aware Memory (SaM) Manycore systems Scalability 

References

  1. 1.
    Becker J, Brändle K, Brinkschulte U, Henkel J, Karl W, Köster T, Wenz M, Wörn H (2006) Digital on-demand computing organism for real-time systems. In: ARCS Workshops, pp 230–245Google Scholar
  2. 2.
    Buchty R, Mattes O, Karl W (2008) Self-aware memory: managing distributed memory in an autonomous multi-master environment. In: Architecture of computing systems—ARCS 2008, Lecture Notes in Computer Science, vol 4934, pp 98–113Google Scholar
  3. 3.
    Duato J (2009) Beyond the power and memory walls: The role of HyperTransport in future system architectures. In: First international workshop on hypertransport research and applications (WHTRA)Google Scholar
  4. 4.
    Fleig T, Mattes O, Karl W (2014) Evaluation of adaptive memory management techniques on the Tilera TILE-Gx Platform. In: 11th workshop on parallel systems and algorithms (PASA 2014), LübeckGoogle Scholar
  5. 5.
    Gries M, Hoffmann U, Konow M, Riepen M (2011) SCC: A flexible architecture for many-core platform research. Comput Sci Eng 13(6):79–83CrossRefGoogle Scholar
  6. 6.
    Heinecke A, Klemm M, Bungartz H-J (2012) From GPGPU to many-core: nvidia fermi and intel many integrated core architecture. Comput Sci Eng 14(2):78–83CrossRefGoogle Scholar
  7. 7.
    Kalray: KALRAYs MPPA (2013) (Multi-Purpose Processor Array). http://www.kalray.eu/products/mppa-manycore/
  8. 8.
    Kephart JO, Chess DM (2003) The vision of autonomic computing. IEEE Comput Soc Press 36(1):41–50CrossRefGoogle Scholar
  9. 9.
    Kramer D, Buchty R, Karl W (2011) Monitoring and self-awareness for heterogeneous, adaptive computing systems. In: Organic Computing - a paradigm shift for complex systems, autonomic systems, vol. 1. Springer, Basel, pp 163–177Google Scholar
  10. 10.
    Landwehr A, Zuckerman S, Gao GR (2013) Toward a Self-aware system for exascale architectures. In: CAPSL Technical Memo 123Google Scholar
  11. 11.
    Lee H, Cho S, Childers BR (2011) CloudCache: expanding and shrinking private caches. In: IEEE 17th international symposium on high performance computer architecture (HPCA), pp 219–230Google Scholar
  12. 12.
    Mathews G, Durrant-Whyte H, Prokopenko M (2007) Decentralized decision making for multiagent systems. In: Advances in applied self-organizing systems. Springer, London, pp 77–104Google Scholar
  13. 13.
    Mattes O (2013) An Autonomous self-optimizing memory system for upcoming manycore architectures. In: Proceedings of the first organic computing doctoral dissertation colloquium (OC-DDC’13). vol 2013–06, Fakultät für Angewandte Informatik der Universität Augsburg, pp 4–7Google Scholar
  14. 14.
    Mattes O, Karl W (2013) Self-aware memory - an autonomous self-optimizing memory system for upcoming manycore architectures. In: Memory architecture and organization Workshop (MeAOW’13), Embedded Systems Week 2013, MontrealGoogle Scholar
  15. 15.
    Mattes O, Schindewolf M, Sedler R, Buchty R, Karl W (2011) Efficient synchronization techniques in a decentralized memory management system enabling shared memory. PARS 2011, Rüschlikon, Switzerland, In: PARS Mitteilungen GI, vol 28, Gesellschaft für Informatik e.VGoogle Scholar
  16. 16.
    Richter U, Mnif M, Branke J, Müller-Schloer C, Schmeck H (2006) Towards a generic observer/controller architecture for organic computing. In: GI Jahrestagung, vol, pp 112–119Google Scholar
  17. 17.
    Schindewolf M, Mattes O, Karl W (2011) Thread creation for self-aware parallel systems. In: Facing the multicore-challenge, vol 6310., Lecture Notes in Computer Science. Springer, Berlin, pp 42–53Google Scholar
  18. 18.
    Taylor MB, Kim J, Miller J, Wentzlaff D, Ghodrat F, Greenwald B, Hoffman H, Johnson P, Lee JW, Lee W, Ma A, Saraf A, Seneski M, Shnidman N, Strumpen V, Frank M, Amarasinghe S, Agarwal A (2002) The Raw microprocessor: a computational fabric for software circuits and general-purpose programs. IEEE Micro 22(2):25–35CrossRefGoogle Scholar
  19. 19.
    Tilera Corporation (2012) TILE-Gx8038 processor specification brief. San Jose, CA. http://www.tilera.com/sites/default/files/productbriefs/TILE-Gx8036_PB033-02_web.pdf

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  1. 1.Institute of Computer Science & Engineering (ITEC)Karlsruhe Institute of Technology (KIT)KarlsruheGermany

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