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Design Automation for Embedded Systems

, Volume 19, Issue 1–2, pp 59–76 | Cite as

The fast evolving landscape of on-chip communication

Selected future challenges and research avenues
  • Davide Bertozzi
  • Giorgos Dimitrakopoulos
  • José Flich
  • Sören Sonntag
Article

Abstract

As multi-core systems transition to the many-core realm, the pressure on the interconnection network is substantially elevated. The Network-on-Chip (NoC) is expected to undertake the expanding demands of the ever-increasing numbers of processing elements, while—at the same time—technological and application constraints increase the pressure for increased performance and efficiency with limited resources. Although NoC research has evolved significantly the last decade, essential questions remain un-answered and call for fresh research ideas and innovative solutions. In this paper, we summarize a selected set of NoC-related research challenges, with the hope to guide future development and trigger high-impact research progress.

Keywords

Network on chip Microarchitecture Physical integration Optical NoCs Wireless NoCs Virtualization 

References

  1. 1.
    Handy J (2011) NoC interconnect improves SoC economics. Objective analysis—semiconductor market researchGoogle Scholar
  2. 2.
    Browne J (2012) On-Chip Communications Network. in SonicsGoogle Scholar
  3. 3.
    Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proceedings of the 38th design automation conference (DAC)Google Scholar
  4. 4.
    Wentzlaff D et al (2007) On-chip interconnection architecture of the tile processor. IEEE Micro, pp 15–31Google Scholar
  5. 5.
    Benini L, De Micheli G (2002) Networks on chips: a new SoC paradigm. IEEE Comput 35(1):7078CrossRefGoogle Scholar
  6. 6.
    De Micheli G, Seiculescu C, Murali S, Benini L and Angiolini F et al (2010) Networks on chips: from research to products. In: 47th design automation conference (DAC 2010)Google Scholar
  7. 7.
    Kim J, Balfour J, Dally WJ (2007) Flattened butterfly topology for on-chip networks. In: Proceedings of IEEE/ACM international symposium on microarchitecture (MICRO)Google Scholar
  8. 8.
    Mishra AK, Vijaykrishnan N, Das CR (2011) A case for heterogeneous on-chip interconnects for cmps. In: Proceedings of the international symposium on computer, architecture, pp 389–400Google Scholar
  9. 9.
    Flich J, Mejia A, Lopez P, Duato J (2007) Region-based routing: An efcient routing mechanism to tackle unreliable hardware in networks on chip. In: International symposium on networks on chip (NOCS)Google Scholar
  10. 10.
    Ma S, Enright Jerger N, Wang Z (2012) Whole packet forwarding: efficient design of fully adaptive routing algorithms for networks-on-chip. In: Proceedigs of the international symposium on high performance computer, architecture, pp 467–478Google Scholar
  11. 11.
    Seo D, Ali A, Lim W-T, Rafique N, Thottethodi M (2005) Near-optimal worst-case throughput routing for two-dimensional mesh networks. In: Proceedings of the 32nd annual international symposium on computer architecture (ISCA ’05). IEEE Computer Society, Washington, DC, pp 432–443Google Scholar
  12. 12.
    Balfour J, Dally WJ (2006) Design tradeoffs for tiled CMP on-chip networks. In: Proceedings of the 20th ACM international conference on supercomputing (ICS)Google Scholar
  13. 13.
    Passas G, Katevenis M, Pnevmatikatos D (2012) Crossbar NoCs are scalable beyond 100 nodes. IEEE transactions on computer-aided design of integrated circuits and systems (TCAD). 31(4):573–585. ISSN: 0278–0070Google Scholar
  14. 14.
    Azimi M, Dai D, Mejia A, Park D, Saharoy R, Vaidya AS (2009) Flexible and adaptive on-chip interconnect for tera-scale architectures. Intel Technol J 13(4):6277Google Scholar
  15. 15.
    Kim J (2009) Low-cost router microarchitecture for on-chip networks. In: International symposiun on microarchitectureGoogle Scholar
  16. 16.
    Salihundam P et al (2010) A 2Tb/s 6x4 mesh network with DVFS and 2.3Tb/s/W router in 45nm CMOS. In: Sympsosium VLSI circuitsGoogle Scholar
  17. 17.
    Vangal SR et al (Jan. 2008) An 80-tile sub-100-W teraFLOPS processor in 65-nm CMOS. IEEE J Solid-State Circuits 43:6–20Google Scholar
  18. 18.
    Peh L-S, Dally WJ (2001) A delay model and speculative architecture for pipelined routers. In: Proceedigs of the 7th international symposium on high-performance computer, architecture (HPCA-7)Google Scholar
  19. 19.
    Mullins RD, West AF, Moore SW (2004) Low-latency virtual-channel routers for on-chip networks. In: Procedings of the international symposium on computer, architecture, pp 188–197Google Scholar
  20. 20.
    Tran AT, Baas BM (2011) RoShaQ: high-performance on-chip router with shared queues. In: IEEE ICCD, pp 232–238Google Scholar
  21. 21.
    Becker DU (2012) Adaptive backpressure: efficient buffer management for on-chip networks. In: IEEE ICCDGoogle Scholar
  22. 22.
    Hassan SM and Yalamanchili S (2013) Centralized buffer router: a low latency, low power router for high radix nocs. In: IEEE/ACM international symposium on network on chipGoogle Scholar
  23. 23.
    Seitanidis I, Psarras A, Dimitrakopoulos G, Nicopoulos C (2014) Elastistore: an elastic buffer architecture for network-on-chip routers. In: Proceedings of design automation and test in Europe (DATE)Google Scholar
  24. 24.
    Michelogiannakis G, Jiang N, Becker D, Dally W.J (2011) Packet chaining: efficient single-cycle allocation for on-chip networks. In: Proceedings IEEE/ACM international symposium on microarchitecture (MICRO), pp 83–94Google Scholar
  25. 25.
    Dimitrakopoulos G et al (2013) Merged switch allocation and traversal in network-on-chip switches. In: IEEE transation on computersGoogle Scholar
  26. 26.
    Roca A, Hernandez C, Flich J, Silla F, Duato J (2013) Silicon-aware distributed switch architecture for on-chip networks. J Syst Archit 59(7):505–515CrossRefGoogle Scholar
  27. 27.
    Balkan A, Qu G, Vishkin U (Oct 2009) Mesh-of-trees and alternative interconnection networks for single-chip parallelism. IEEE Trans VLSI Syst 17(10):1419–1432Google Scholar
  28. 28.
    Saponara S, Bacchillone T, Petri E, Fanucci L, Locatelli R, Coppola M Design of a NoC interface macrocell with hardware support of advanced networking functionalities. In: IEEE transactions on computersGoogle Scholar
  29. 29.
    Yang X, Qing-li Z, Fang-fa F, Ming-yan Y, Cheng L (2007) NISAR: an AXI compliant on-chip NI architecture offering transaction reordering processing. In: Proceedings of the 7th international conference ASIC ASICON 07, p 890893Google Scholar
  30. 30.
    Radulescu A, Dielissen J, Pestana SG, Gangwal OP, Rijpkema E, Wielage P, Goossens K (2005) An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration. IEEE Trans Comput Aided Design Integr Circuits Syst 24(1):417Google Scholar
  31. 31.
    Ebrahimi M, Daneshtalab M, Liljeberg P, Plosila J, Tenhunen H (2010) A high-performance network interface architecture for NoCs using reorder buffer sharing. In: Proceedings of the 18th Euromicro international parallel, distributed and network-based processing (PDP) conference, p 546550Google Scholar
  32. 32.
    Kavadias S, Katevenis M, Pnevmatikatos D (2011) Network interface design for explicit communication in chip multiprocessors, chapter 10. In: Flich J, Bertozzi D (eds) designing network-on-chip architectures in the nanoscale era. CRC Press–Taylor & Francis Groupa, pp 325–351. ISBN: 978-1-4398-3710-8Google Scholar
  33. 33.
    Fingeroff M (2010) High-level synthesis blue book. Xlibris CorpGoogle Scholar
  34. 34.
    Coussy P, Morawiec A (2008) High-level synthesis: from algorithm to digital circuit. SpringerGoogle Scholar
  35. 35.
    Shacham O, Azizi O, Wachs M, Richardson S, Horowitz M (2010) Rethinking digital design: why design must change. IEEE Micro 30(6): 9–24Google Scholar
  36. 36.
    Kim G, Lee MM, Kim J, Lee JW, Abts D, Marty M (2014) Low-overhead network-on-chip support for location-oblivious task placement. IEEE Trans Comput 99:1 PrePrintsMathSciNetGoogle Scholar
  37. 37.
    Itoh K (2009) Adaptive circuits for the 0.5-V nanoscale CMOS Era. In: ISSCCGoogle Scholar
  38. 38.
    International Technology Roadmap for Semiconductors 2011. System Drivers, Figure SYSD3Google Scholar
  39. 39.
    Howard J et al (2010) A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS. In: ISSCC, pp 108–109Google Scholar
  40. 40.
    Kim W, Gupta MS, Wei GY, Brooks D (2008) System level analysis of fast, per-core DVFS using on-chip switching regulators. In: International symposiun on high-performance computer, architectureGoogle Scholar
  41. 41.
    Isci C, Buyuktosunoglu A, Cher C, Bose P and Martonosi M (2006) An analysis of efficient multi-core global power management policies: maximizing performance for a given power budget. In: International symposium on microarchitecture, pp 347–358Google Scholar
  42. 42.
    Jain R, Geuskens B, Kim S, Khellah M, Kulkarni J, Tschanz J, De V (2014) A 0.45-1V fully-integrated distributed switched capacitor DC-DC converter with high density MIM capacitor in 22 nm tri-gate CMOS. IEEE J Solid-State Circuit PP(99):1–11Google Scholar
  43. 43.
    Robert Hilbrich J, van Kampenhout R (2011) Partitioning and task transfer on noC-based many-core processors in the avionics domain. Softwaretechnik-Trends 31(3)Google Scholar
  44. 44.
    Trivio Francisco, Snchez Jos L, Alfaro Francisco J, Flich Jos (2012) Network-on-chip virtualization in chip-multiprocessor systems. J Syst Archit Embed Syst Design 58(3–4):126–139CrossRefGoogle Scholar
  45. 45.
    Sem-Jacobsen FO, Rodrigo Mocholi S, Strano A, Skeie T, Bertozzi D and Gilabert F (2013) Enabling Power Efficiency through Dynamic Rerouting On-Chip. ACM Trans Embed Comput Syst (TECS) 12(4):1–111:23Google Scholar
  46. 46.
    Strano A, Ludovici D, Pavlidis V, Angiolini F, Krstic M, Bertozzi D (2011) Synchronization Challenge, chapter 6. In: Flich J, Bertozzi D (eds) Designing network on-chip architectures in the nanoscale era. Chapman and Hall/CRC Press, London Taylor and Francis [distributor]Google Scholar
  47. 47.
    Loi I, Angiolini F, Benini L (2008) Developing mesochronous synchronizers to enable 3D NoCs. In: Proceedings of the design, automation and test in Europe conference, pp 1414–1419Google Scholar
  48. 48.
    Saponara S, Cecchini T, Sechi F, Fanucci L (2009) Pin-limited frequency converter IP bridge for efficient communication of automotive IC sensors with off-chip ECUs. In: IEEE international workshop on intelligent data acquisition and advanced computing systems: technology and applications, pp 167–171Google Scholar
  49. 49.
    Tatenguem HF et al (2011) Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study. In: Proceedings of the 4th international workshop on network on chip architectures, pp 37–42Google Scholar
  50. 50.
    Krstic M et al (2012) Evaluation of GALS methods in scaled CMOS technology: moonrake chip experience. IJERTCS 3(4):1–18MathSciNetGoogle Scholar
  51. 51.
    Ludovici D, Strano A, Bertozzi D, (2009) Architecture design principles for the integration of synchronization interfaces into network-on-chip switches. In: 2nd international workshop on network on chip architectures, pp 31–36Google Scholar
  52. 52.
    Vangal S et al (2007) An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS. In: ISSCC, pp 98–589Google Scholar
  53. 53.
    Vivek De et al (2014) A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 1616 network-on-chip in 22nm Tri—Gate CMOS. In: ISSCCGoogle Scholar
  54. 54.
    Nowick SM, Singh M (2011) High-performance asynchronous pipelines: an overview. IEEE Design Test Comput 28(5):8–22CrossRefGoogle Scholar
  55. 55.
    Yakovlev A, Vivet P, Renaudin M (2013) Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools. In: Design, automation & test in Europe conference & exhibition (DATE), pp 1715–1724Google Scholar
  56. 56.
    Moreira MT, Magalhaes FG, Gibiluka M, Hessel FP, Calazans NLV (2013) BaBaNoC: an asynchronous network-on-chip described in Balsa. In: International symposium on rapid system prototyping (RSP), pp 37–43Google Scholar
  57. 57.
    Lee W, Vij VS, Thatcher AR, Stevens KS Design of low energy, high performance synchronous and asynchronous 64-point FFT. In: DATE ’13 proceedings of the conference on design, automation and test in, Europe, pp 242–247Google Scholar
  58. 58.
    Plana LA et al (2011) SpiNNaker: design and implementation of a GALS multicore system-on-chip. ACM JETC 7(4):17:1–17:18MathSciNetGoogle Scholar
  59. 59.
    Thonnart Y, Vivet P, Clermidy F (2010) A fully-asynchronous low-power framework for GALS NoC integration. In: DATE, pp 33–38Google Scholar
  60. 60.
    Beerel PA, Dimou GD, Lines AM (2011) Proteus: an ASIC flow for GHz asynchronous designs. IEEE Design Test Comput 28(1):36–51CrossRefGoogle Scholar
  61. 61.
    Thonnart Y, Beigne E, Vivet P (2012) A pseudo-synchronous implementation flow for WCHB QDI asynchronous circuits. In: 18th IEEE international symposium on asynchronous circuits and systems (ASYNC), pp 73–80Google Scholar
  62. 62.
    Gebhardt D, You J, Stevens KS (2011) Design of an energy-efficient asynchronous NoC and its optimization tools for heterogeneous SoCs. IEEE Trans Comput Aided Design Integr Circuits Syst 30(9):1387–1399Google Scholar
  63. 63.
    Imai M, Yoneda T, (2011) Improving dependability and performance of fully asynchronous on-chip networks. In: 17th IEEE international symposium on asynchronous circuits and systems (ASYNC), pp 65–76Google Scholar
  64. 64.
    Ghiribaldi A, Bertozzi D, Nowick SM (2013) A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems. In: Design, automation & test in Europe conference & exhibition (DATE), pp 332–337Google Scholar
  65. 65.
    Clermidy F et al (2010) MAGALI: a network-on-chip based multi-core system-on-chip for MIMO 4G SDR. In: IEEE international conference on IC design and technology (ICICDT), pp 74–77Google Scholar
  66. 66.
    Beigne E et al (2009) An asynchronous power aware and adaptive NoC based circuit. IEEE J Solid-State Circuits 44(4):1167–1177CrossRefGoogle Scholar
  67. 67.
    ETP4HPC Strategic Research Agenda. http://www.etp4hpc.eu/
  68. 68.
    International technology roadmap for semiconductors 2011. InterconnectGoogle Scholar
  69. 69.
    Pasricha S, Dutt N (2008) Trends in emerging on-chip interconnect technologies. IPSJ Trans Syst LSI Design Methodol 1:2–7CrossRefGoogle Scholar
  70. 70.
    Carloni LP et al (2009) Networks-on-chip in emerging interconnect paradigms: advantages and challenges. In: Proceedings of 3rd ACM/IEEE international symposium networks-on-chip, pp 93–102Google Scholar
  71. 71.
    Kachris Christoforos, Tomkos Ioannis (2012) A survey on optical interconnects for data centers. IEEE Commun Surv Tutor 14(4):1021–1036CrossRefGoogle Scholar
  72. 72.
    Kirman N et al (2006) Leveraging optical technology in future bus-based chip multiprocessors. In: MICROGoogle Scholar
  73. 73.
    Batten C et al (2008) Building manycore processor-to-dram networks with monolithic silicon photonics. In: Hot interconnects, pp 21–30Google Scholar
  74. 74.
    Pan Y, Kumar P, Kim J, Memik G, Zhang Y, Choudhary AN (2009) Firefly: illuminating future network-on-chip with nanophotonics. In: ISCA, pp 429–440Google Scholar
  75. 75.
    Vantrease D, Binkert N. L, Schreiber R, Lipasti MH (2009) Light speed arbitration and flow control for nanophotonic interconnects. In: MICRO’09, pp 304–315Google Scholar
  76. 76.
    Kurian G, Miller JE, Psota J, Eastep J, Liu J, Michel J, Kimerling LC, Agarwal A (2010) ATAC: a 1000-core cache-coherent processor with on-chip optical network. In: PACT’10, pp 477–488Google Scholar
  77. 77.
    Vantrease D et al (2008) Corona: system implications of emerging nanophotonic technology. In: ISCAGoogle Scholar
  78. 78.
    Cianchetti MJ, Kerekes JC, Albonesi DH (June 2009) Phastlane: a rapid transit optical routing network. SIGARCH Comput. Archit. News 37:441–450Google Scholar
  79. 79.
    Pan Y, Kim J, Memik G (2010) Flexishare: channel sharing for an energy-efficient nanophotonic crossbar. In: HPCA, pp 1–12Google Scholar
  80. 80.
    Shacham A, Lee BG, Biberman A, Bergman K, Carloni LP (2007) Photonic NoC for DMA communications in chip multiprocessors. In: Hot interconnectsGoogle Scholar
  81. 81.
    Chan J, Hendry G, Biberman A, Bergman K, Carloni LP (2010) Phoenixsim: a simulator for physical-layer analysis of chip-scale photonic interconnection networks. DATEGoogle Scholar
  82. 82.
    Hendry G et al (2009) Analysis of photonic networks for a chip multi-processor using scientific applications, DATE, 2010. In: Proceedings of the third international symposium on networks-on-chip (NOCS)Google Scholar
  83. 83.
    Ortn Obn M, Ramini L, Tatanguem Fankem H, Vinals-Yufera V, Bertozzi D (2014) A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip. In: Proceedings of GLSVLSI symposiumGoogle Scholar
  84. 84.
    Ramini L, Grani P, Tatenguem Fankem H, Ghiribaldi A, Bartolini S, Bertozzi D (2014) Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline. In: Proceedings of DATEGoogle Scholar
  85. 85.
    Kurian G et al (2012) Cross-layer energy and performance evaluation of a nanophotonic manycore processor system using real application workloads. In: IEEE 26th international parallel & distributed processing symposium (IPDPS), pp 1117–1130Google Scholar
  86. 86.
    Chang MF et al (2008) CMP network-on-chip overlaid with multi-band RF-interconnect. In: Proceedings of IEEE international symposium on high-performance computer architecture (HPCA), Feb 16–20, pp 191–202Google Scholar
  87. 87.
    Zhao D, Wang Y (2008) SD-MAC: design and synthesis of A hardware-efficient collision-free QoS-aware MAC protocol for wireless network-on-chip. IEEE Trans Comput 57(9):1230–1245MathSciNetCrossRefGoogle Scholar
  88. 88.
    Lee SB et al (2009) A scalable micro wireless interconnect structure for CMPs. In: Proceedings of ACM annual international conference on mobile computing and networking (MobiCom), pp 20–25Google Scholar
  89. 89.
    Kempa K et al (2007) Carbon nanotubes as optical antennae. Adv Mater 19:421–426CrossRefGoogle Scholar
  90. 90.
    Deb S, Ganguly A, Pande PP, Belzer B, Heo D (2012) Wireless NoC as interconnection backbone for multicore chips: promises and challenges. IEEE J Emerg Selected Topics Circuits Syst 2(2):228–239Google Scholar
  91. 91.
    Weiss SM, Molinari M, Fauchet PM (2003) Temperature stability for silicon-based photonic band-gap structures. Appl Phys Lett 83(10):1980–1982CrossRefGoogle Scholar
  92. 92.
    Yu X et al (2011) A wideband body-enabled millimeter-wave transceiver for wireless network-on-chip. In: Proceedings of the 54th IEEE midwest symposium on circuits and system, pp 1–4Google Scholar
  93. 93.
    Lee SB et al (2009) A scalable micro wireless interconnect structure for CMPs. In: Proceedings of the ACM annual international conference on mobile computing and network. (MobiCom), pp 20–25Google Scholar
  94. 94.
    Ganguly A et al (2011) Scalable hybrid wireless network-on-chip architectures for multi-core systems. IEEE Trans. Comput 60(10):1485–1502Google Scholar
  95. 95.
    Batten C, Joshi A, Stojanovic V, Asanovic K (2012) Designing chip-level nanophotonic interconnection networks. IEEE J Emerg Selected Topics Circuits Syst 2(2):137–153Google Scholar
  96. 96.
    Leu JC, Stojanovic V, (2011) Injection-locked clock receiver for monolithic optical link in 45nm. Asian solid-state circuits conference, Jeju, Korea, pp 149–152Google Scholar
  97. 97.
    Ramini L, Grani P, Bartolini S, Bertozzi D (2013) Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis. In: DATE, pp 1589–1594Google Scholar
  98. 98.
    Le Beux S, Trajkovic J, O’Connor I, Nicolescu G (2011) Layout guidelines for 3D architectures including optical ring network-on-chip (ORNoC). VLSI-SoC, pp 242–247Google Scholar
  99. 99.
    DiTomaso D et al (2011) iWise: inter-routerwireless scalable express channels for network-on-chips (NoCs) architecture. In: Proceedings of the annual symposium on high performance interconnects, pp 11–18Google Scholar
  100. 100.
    Deb S et al (2010) Enhancing performance of network-on-Chip architectures with millimeter-wave wireless interconnects. In: Proceedings of the IEEE international conference on ASAP, pp 73–80Google Scholar
  101. 101.
    Zhao D et al (2011) Design of multi-channel wireless NoC to improve on-chip communication capacity. In: Proceedings of the 5th ACM/IEEE international symposium on networks-on-chip, pp 177–184Google Scholar
  102. 102.
    Wang C et al (2011) A wireless network-on-chip design for multicore platforms. In: Proceedings of the 19th international euromicro conference on parallel, distributed network-based process., pp 409–416Google Scholar
  103. 103.
    Chang K et al (2012) Performance evaluation and design trade-offs for wireless network-on-chip architectures. ACM J Emerg Technol Comput Syst 8:1–23:25Google Scholar
  104. 104.
    Deb S et al (2012) Design of an efficient NoC architecture using millimeter-wave wireless links. In: Proceedings of the IEEE international symposium on quality electron. Design (ISQED), pp 165–172Google Scholar
  105. 105.
    Ganguly A et al (2011) Complex network inspired fault-tolerant NoC architectures with wireless links. In: Proceedings of the 5th ACM/IEEE international symposium on networks-on-chip, pp 1485–1502Google Scholar
  106. 106.
    Ganguly A et al (2011) A unified error control coding scheme to enhance the reliability of a hybrid wireless Network-on-Chip. In: Proceedings of the IEEE international symposium defect fault tolerance VLSI nanotechnology system, pp 277–285Google Scholar
  107. 107.
    Boos A, Ramini L, Schlichtmann U, Bertozzi D (2013) PROTON: an automatic place-and-route tool for optical Networks-on-Chip. ICCAD, pp 138–145Google Scholar
  108. 108.
    Deb S, Chang K, Ganguly A, Pande P (2010) Comparative performance evaluation of wireless and optical NoC architectures. SoCC 487–492Google Scholar
  109. 109.

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Davide Bertozzi
    • 1
  • Giorgos Dimitrakopoulos
    • 2
  • José Flich
    • 3
  • Sören Sonntag
    • 4
  1. 1.University of FerraraFerraraItaly
  2. 2.Democritus University of ThraceXanthiGreece
  3. 3.Universitat Politècnica de ValènciaValenciaSpain
  4. 4.Intel CorpMunichGermany

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