Design Automation for Embedded Systems

, Volume 16, Issue 4, pp 339–361 | Cite as

High-level customization framework for application-specific NoC architectures

  • Iraklis Anagnostopoulos
  • Alexandros Bartzas
  • Iason Filippopoulos
  • Dimitrios Soudris
Article

Abstract

Network-on-Chip (NoC) has been recognized as the new paradigm to interconnect and organize a high number of cores. NoCs address global communication issues in System-on-Chips (SoC) involving communication-centric design and implementation of scalable communication structures evolving application-specific NoC design as a key challenge to modern SoC design. In this paper we present a SystemC customization framework and methodology for automatic design and evaluation of regular and irregular NoC architectures. The presented framework also supports application-specific optimization techniques such as priority assignment, node clustering and buffer sizing. Experimental results show that generated regular NoC architectures achieve an average of 5.5 % lower communication-cost compared to other regular NoC designs while irregular NoCs proved to achieve on average 4.5×higher throughput and 40 % network delay reduction compared to regular mesh topologies. In addition, employing a buffer sizing algorithm we achieve a reduction in network’s power consumption by an average of 45 % for both regular and irregular NoC design flow.

Keywords

Network-on-Chip Design methodology Automation framework Mapping Priorities assignment Buffer sizing Regular and irregular topologies 

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Iraklis Anagnostopoulos
    • 1
  • Alexandros Bartzas
    • 1
  • Iason Filippopoulos
    • 2
  • Dimitrios Soudris
    • 1
  1. 1.School of Electrical and Computer EngineeringNational Technical University of Athens (NTUA)AthensGreece
  2. 2.Department of Electronics and TelecommunicationsNorwegian University of Science and Technology (NTNU)TrondheimNorway

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