Design Automation for Embedded Systems

, Volume 17, Issue 2, pp 343–375 | Cite as

Symbolic system-level design methodology for multi-mode reconfigurable systems

  • Stefan Wildermann
  • Felix Reimann
  • Daniel Ziener
  • Jürgen Teich
Article

Abstract

Modern embedded systems provide a variety of functionality as operational modes, each corresponding to a mutually exclusive phase of operation. This paper provides a system level design methodology tailored for such multi-mode systems. By incorporating knowledge about the temporal behavior, it is possible to share hardware by means of partial reconfiguration on sophisticated Field Programmable Gate Arrays (FPGAs), and thus, reduce costs and improve performance. The presented methodology is based on an exploration model, which specifies the temporal behavior of the system functionality as well as the architectural characteristics of nowadays reconfigurable technology. We develop a symbolic encoding of this system specification, which enables unified system synthesis by applying sophisticated optimization techniques to perform allocation, binding, placement of partially reconfigurable modules, and routing the on-chip communication.

The presented system-level design methodology complies with the state-of-the-art synthesis tools and communication technologies for partially reconfigurable systems. We demonstrate this by experiments on test cases from the image processing domain applying state-of-the-art technology. The results give evidence of the efficiency of the methodology and show the superiority in terms of runtime and quality of the found solutions compared to existing system-level synthesis approaches.

Keywords

Design space exploration System level design Partial reconfiguration Field-programmable gate arrays 

References

  1. 1.
    Barth P (1996) Logic-based 0-1 constraint programming. Kluwer Academic, Norwell CrossRefMATHGoogle Scholar
  2. 2.
    Becker T, Luk W, Cheung PYK (2010) Energy-aware optimisation for run-time reconfiguration. In: Proc. of FCCM 2010, May 2010, pp 55–62 Google Scholar
  3. 3.
    Blickle T, Teich J, Thiele L (1998) System-level synthesis using evolutionary algorithms. Des Autom Embed Syst 3:23–58 CrossRefGoogle Scholar
  4. 4.
    Buttazzo GC (2005) Hard real-time computing systems. Springer, Berlin CrossRefMATHGoogle Scholar
  5. 5.
    Davis M, Logemann G, Loveland D (1962) A machine program for theorem-proving. Commun ACM 5:394–397 CrossRefMATHMathSciNetGoogle Scholar
  6. 6.
    ElGindy HA, Schröder H, Spray A, Somani AK, Schmeck H (1996) RMB—a reconfigurable multiple bus network. In: Proceedings of the symposium on high-performance computer architecture (HPCA), pp 108–117, 3–7 CrossRefGoogle Scholar
  7. 7.
    GlaßM, Lukasiewycz M, Teich J, Bordoloi UD, Chakraborty S (2009) Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis. In: Proceedings of the design automation conference (DAC), San Francisco, USA, July 2009, pp 43–46 Google Scholar
  8. 8.
    Hagemeyer J, Kettelhoit B, Koester M, Porrmann M (2007) Design of homogeneous communication infrastructures for partially reconfigurable FPGAs. In: Proceedings of the international conference on engineering of reconfigurable systems and algorithms (ERSA), pp 238–247 Google Scholar
  9. 9.
    Hagemeyer J, Kettelhoit B, Koester M, Porrmann M (2007) INDRA—integrated design flow for reconfigurable architectures. In: Proceedings of the design, automation and test in Europe (DATE) Google Scholar
  10. 10.
    Huang L, Xu Q (2010) Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint. In: Proceedings of the design, automation and test in Europe (DATE), pp 1584–1589 Google Scholar
  11. 11.
    Jejurikar R, Pereira C, Gupta R (2004) Leakage aware dynamic voltage scaling for real-time embedded systems. In: Proc of DAC 2004, pp 275–280 Google Scholar
  12. 12.
    Kestur S, Davis JD, Williams O (2010) BLAS comparison on FPGA, CPU and GPU. In: Proc of VLSI 2010, July 2010, pp 134–139 Google Scholar
  13. 13.
    Kienhuis B, Deprettere E, Vissers K, van der Wolf P (1997) An approach for quantitative analysis of application-specific dataflow architectures. In: Proceedings of the international conference on application-specific systems, architectures and processors (ASAP), ASAP ’97, July 1997, pp 338–349 CrossRefGoogle Scholar
  14. 14.
    Koch D, Beckhoff C, Teich J (2008) ReCoBus-builder—a novel tool and technique to build statically and dynamically reconfigurable systems for FPGAs. In: Proceedings of the international conference on field-programmable logic and applications (FPL), September 2008, pp 119–124 Google Scholar
  15. 15.
    Koch D, Beckhoff C, Teich J (2009) Minimizing internal fragmentation by fine-grained two-dimensional module placement for runtime reconfigurable systems. In: Proceedings of the symposium on field-programmable custom computing machine (FCCM), pp 251–254 Google Scholar
  16. 16.
    Koch D, Haubelt C, Teich J (2008) Efficient reconfigurable on-chip buses for FPGAs. In: Proceedings of the symposium on field-programmable custom computing machine (FCCM), April 2008, pp 287–290 Google Scholar
  17. 17.
    Koester M, Luk W, Hagemeyer J, Porrmann M, Rückert U (2011) Design optimizations for tiled partially reconfigurable systems. IEEE Trans Very Large Scale Integr Syst 19(6):1048–1061 CrossRefGoogle Scholar
  18. 18.
    Laumanns M, Thiele L, Deb K, Zitzler E (2002) Combining convergence and diversity in evolutionary multiobjective optimization. Evol Comput 10:263–282 CrossRefGoogle Scholar
  19. 19.
    Le Berre D, Parrain A (2010) The SAT4J library, release 2.2, system description. J Satisf Boolean Model Comput 7:59–64 Google Scholar
  20. 20.
    Lukasiewycz M (2010) Modeling, analysis, and optimization of automotive networks. Dissertation, University of Erlangen-Nuremberg, Germany. Cuvillier Verlag, Göttingen Google Scholar
  21. 21.
    Lukasiewycz M, GlaßM, Haubelt C, Teich J (2007) SAT-decoding in evolutionary algorithms for discrete constrained optimization problems. In: Proceedings of the Congress on evolutionary computation (CEC), Singapore, Singapore, September 2007, pp 935–942 Google Scholar
  22. 22.
    Lukasiewycz M, GlaßM, Haubelt C, Teich J (2008) Efficient symbolic multi-objective design space exploration. In: Proceedings of the Asia and South pacific design automation conference (ASPDAC), pp 691–696 Google Scholar
  23. 23.
    Lukasiewycz M, GlaßM, Haubelt C, Teich J, Regler R, Lang B (2008) Concurrent topology and routing optimization in automotive network integration. In: Proceedings of the design automation conference (DAC), Anaheim, USA, June 2008, pp 626–629 Google Scholar
  24. 24.
    Lukasiewycz M, GlaßM, Reimann F, Teich J (2011) Opt4J—a modular framework for meta-heuristic optimization. In: Proceedings of the genetic and evolutionary computing conference (GECCO), Dublin, Ireland Google Scholar
  25. 25.
    Lukasiewycz M, GlaßM, Teich J (2009) Exploiting data-redundancy in reliability-aware networked embedded system design. In: Proceedings of the international conference on Hardware/Software codesign and system synthesis (CODES+ISSS), pp 229–238 Google Scholar
  26. 26.
    Lukasiewycz M, Streubühr M, GlaßM, Haubelt C, Teich J (2009) Combined system synthesis and communication architecture exploration for MPSoCs. In: Proceedings of the design, automation and test in Europe (DATE), pp 472–477 Google Scholar
  27. 27.
    Lysaght P, Blodget B, Mason J, Young J, Bridgford B (2006) Invited paper: enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration of Xilinx FPGAs. In: Proceedings of the international conference on field-programmable logic and applications (FPL), pp 1–6 Google Scholar
  28. 28.
    Müller R, Teubner J (2009) FPGA: what’s in it for a database? In: SIGMOD, pp 999–1004 CrossRefGoogle Scholar
  29. 29.
    Oetken A, Wildermann S, Teich J, Koch D (2010) A bus-based SoC architecture for flexible module placement on reconfigurable FPGAs. In: Proceedings of the international conference on field-programmable logic and applications (FPL), pp 234–239 Google Scholar
  30. 30.
    Reimann F, GlaßM, Haubelt C, Eberl M, Teich J (2010) Improving platform-based system synthesis by satisfiability modulo theories solving. In: Proceedings of the eighth IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, CODES/ISSS ’10, pp 135–144 CrossRefGoogle Scholar
  31. 31.
    Schmitz MT, Al-Hashimi BM, Eles P (2003) A co-design methodology for energy-efficient multi-mode embedded systems with consideration of mode execution probabilities. In: Proceedings of the design, automation and test in Europe (DATE), pp 960–965 Google Scholar
  32. 32.
    Schmitz MT, Al-Hashimi BM, Eles P (2005) Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities. IEEE Trans Comput-Aided Des Integr Circuits Syst 24(2):153–169 CrossRefGoogle Scholar
  33. 33.
    Sheini HM, Sakallah KA (2006) Pueblo: A hybrid pseudo-boolean SAT solver. J Sat, Boolean Mod Comput, 165–189 Google Scholar
  34. 34.
    Sironi F, Triverio M, Hoffmann H, Maggio M, Santambrogio MD (2010) Self-aware adaptation in FPGA-based systems. In: Proceedings of the international conference on field-programmable logic and applications (FPL), September 2010, pp 187–192 Google Scholar
  35. 35.
    Wildermann S, Angermeier J, Sibirko E, Teich J (2012) Placing multi-mode streaming applications on dynamically partially reconfigurable architectures. International Journal of Reconfigurable Computing Google Scholar
  36. 36.
    Wildermann S, Oetken A, Teich J, Salcic Z (2010) Self-organizing computer vision for robust object tracking in smart cameras. In: Proceedings of international conference on autonomic and trusted computing (ATC). LNCS. Springer, Berlin, pp 1–16 CrossRefGoogle Scholar
  37. 37.
    Wildermann S, Reimann F, Ziener D, Teich J (2011) Symbolic design space exploration for multi-mode reconfigurable systems. In: Proceedings of the international conference on Hardware/Software codesign and system synthesis (CODES+ISSS), pp 129–138 Google Scholar
  38. 38.
    Wildermann S, Teich J, Ziener D (2011) Unifying partitioning and placement for SAT-based exploration of heterogeneous reconfigurable SoCs. In: Proceedings of the international conference on field-programmable logic and applications (FPL), pp 429–434 Google Scholar

Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  • Stefan Wildermann
    • 1
  • Felix Reimann
    • 1
  • Daniel Ziener
    • 1
  • Jürgen Teich
    • 1
  1. 1.University of Erlangen-NurembergErlangenGermany

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