Design Automation for Embedded Systems

, Volume 14, Issue 2, pp 75–103 | Cite as

A scheduler synthesis methodology for joint SW/HW design exploration of SoC

  • Ismail Assayad
  • Sergio Yovine


The introduction of high-performance applications such as multimedia applications into SoCs led the manufacturers to provide embedded SoCs able to offer an important computing power which makes it possible to answer the increasing requirements of future evolutions of these applications. One of the adopted solutions is the use of multiprocessor SoCs. In this paper, we present a joint SW/HW design exploration methodology for multiprocessor SoCs. The system model relies on transaction-level component-based models for modeling parallel software and multiprocessor hardware. Our proposal comprises two original points. First, we propose a composable software-level scheduler constraints synthesis technique. Second, we present a combined software-level and exploratory hardware-level schedulers. The methodology has the advantage of combining real-time requirements of software with effective exploitation of multiprocessor hardware. We describe and apply the methodology to synthesize a scheduler of a slice-based MPEG-4 video encoder on the multiprocessor Cake SoCs.


Multiprocessor System-On-Chips (SoCs) SW/HW design Scheduling Exploration Real-time requirements 


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© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.ENSEMUniversity of Hassan II Ain ChockOasis CasablancaMorocco
  2. 2.Departamento de ComputacionUniversidad de Buenos Aires, and Researcher at CONICETBuenos AiresArgentina

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