Cache-aware optimization of BAN applications

  • Lei Ju
  • Yun Liang
  • Samarjit Chakraborty
  • Tulika Mitra
  • Abhik Roychoudhury


Body-area sensor network or BAN-based health monitoring is increasingly becoming a popular alternative to traditional wired bio-monitoring techniques. However, most biomonitoring applications need continuous processing of large volumes of data, as a result of which both power consumption and computation bandwidth turn out to be serious constraints for sensor network platforms. This has resulted in a lot of recent interest in design methods, modeling and software analysis techniques specifically targeted towards BANs and applications running on them. In this paper we show that appropriate optimization of the application running on the communication gateway of a wireless BAN and accurate modeling of the microarchitectural details of the gateway processor can lead to significantly better resource usage and power savings. In particular, we propose a method for deriving the optimal order in which the different sensors feeding the gateway processor should be sampled, to maximize cache reuse. In addition, we also investigate the effects on cache reuse of different memory layouts of the code processing the different sensor data. The joint optimization of code layout and the order in which the different sensors should be sampled—in order to maximize code cache reuse—turns out to be a difficult combinatorial optimization problem. But our experiments show that optimizing the sampling order of the sensors has a much larger influence on cache reuse, compared to the effects that different code layouts have. Based on this, we also propose a heuristic that obtains near-optimal solutions in jointly optimizing both code layout as well the sensor sampling order. Our case study using a faint fall detection application—from the geriatric care domain—which is fed by a number of smart sensors to detect physiological and physical gait signals of a patient show very attractive power consumption in the underlying processor. Alternatively, our method can be used to improve the sampling frequency of the sensors, leading to higher reliability and better response time of the application.


Health monitoring Body-area sensor networks Timing analysis Cache modeling 


  1. 1.
    Austin T, Larson E, Ernst D (2002) SimpleScalar: An infrastructure for computer system modeling. IEEE Comput 35(2) Google Scholar
  2. 2.
    Brooks D, Tiwari V, Martonosi M (2000) Wattch: A framework for architectural-level power analysis and optimizations. In: ISCA Google Scholar
  3. 3.
    Dasgupta S, Papadimitriou CH, Vazirani U (2006) Algorithms. McGraw-Hill, New York Google Scholar
  4. 4.
    DeVaul RW et al (2003) MIThril 2003: Applications and architecture. In: International symposium on wearable computers Google Scholar
  5. 5.
    Edmison J et al (2006) E-Textile based automatic activity diary for medical annotation and analysis. In: International workshop on wearable and implantable body sensor networks Google Scholar
  6. 6.
    Al Khatib I et al (2006) A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: Architectural design space exploration. In: DAC Google Scholar
  7. 7.
    Farella E et al (2006) A wireless body area sensor network for posture detection. In: IEEE symposium on computers and communications Google Scholar
  8. 8.
    Ghosh A, Givargis T (2004) Cache optimization for embedded processor cores: An analytical approach. ACM Trans Des Autom Electron Syst 9(4) Google Scholar
  9. 9.
    Gupta P, Kahng AB, Mantik S (2005) Routing-aware scan chain ordering. ACM Trans Des Autom Electron Syst 10(3) Google Scholar
  10. 10.
    Jafari R et al (2005) Adaptive and fault tolerant medical vest for life-critical medical monitoring. In: ACM symposium on applied computing Google Scholar
  11. 11.
    Jafari R et al (2005) Wireless sensor networks for health monitoring. In: International conference on mobile and ubiquitous systems Google Scholar
  12. 12.
    Kao J-C, Marculescu R (2006) On optimization of e-textile systems using redundancy and energy-aware routing. IEEE Trans Comput 55(6) Google Scholar
  13. 13.
    Al Khatib I et al (2007) Performance analysis and design space exploration for high-end biomedical applications: Challenges and solutions. In: CODES+ISSS Google Scholar
  14. 14.
    Li Y, Wolf W (1999) Hardware/software co-synthesis with memory hierarchies. IEEE Trans Comput-Aided Des Integrated Circuits Syst 18(10):1405–1417 CrossRefGoogle Scholar
  15. 15.
    Lokuciejewski P, Falk H, Marwedel P (2008) WCET-driven cache-based procedure positioning optimizations. In: 20th Euromicro conference on real-time systems (ECRTS) Google Scholar
  16. 16.
    Negi HS, Mitra T, Roychoudhury A (2003) Accurate estimation of cache-related preemption delay. In: CODES+ISSS Google Scholar
  17. 17.
    Nielson F, Nielson HR, Hankin C (2004) Principles of program analysis. Springer, Berlin Google Scholar
  18. 18.
    Panda PR, Dutt ND, Nicolau A (1997) Memory data organization for improved cache performance in embedded processor applications. ACM Trans Des Autom Electron Syst 2(4) Google Scholar
  19. 19.
    Park S, Mackenzie K, Jayaraman S (2002) The wearable motherboard: A framework for personalized mobile information processing (PMIP). In: DAC Google Scholar
  20. 20.
    Pettis K, Hansen RC (1990) Profile guided code positioning. ACM SIGPLAN Not 25(6) Google Scholar
  21. 21.
    Tomiyama H, Yasuura H (1997) Code Placement Techniques for Cache Miss Rate Reduction. ACM Trans Des Autom Electron Syst 2(4) Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • Lei Ju
    • 1
  • Yun Liang
    • 1
  • Samarjit Chakraborty
    • 2
  • Tulika Mitra
    • 1
  • Abhik Roychoudhury
    • 1
  1. 1.Department of Computer ScienceNational University of SingaporeSingaporeSingapore
  2. 2.Institute for Real-Time Computer SystemsTU MunichMunichGermany

Personalised recommendations