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Design Automation for Embedded Systems

, Volume 9, Issue 1, pp 5–18 | Cite as

Optimizing Leakage Energy Consumption in Cache Bitlines

  • Soontae Kim
  • Narayanan Vijaykrishnan
  • Mahmut Kandemir
  • Mary Jane Irwin
Article

Abstract

As technology scales down into deep-submicron, leakage energy is becoming a dominant source of energy consumption. Leakage energy is generally proportional to the area of a circuit and caches constitute a large portion of the die area. Therefore, there has been much effort to reduce leakage energy in caches. Most techniques have been targeted at cell leakage energy optimization. Bitline leakage energy is critical as well. To this end, we propose a predictive precharging scheme to reduce bitline leakage energy consumption. Results show that energy savings are significant with little performance degradation. Also, our predictive precharging is more beneficial in more aggressively scaled technologies.

Keywords

leakage energy caches predictive precharging 

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Copyright information

© Springer Science + Business Media, Inc. 2004

Authors and Affiliations

  • Soontae Kim
    • 1
  • Narayanan Vijaykrishnan
    • 2
  • Mahmut Kandemir
    • 2
  • Mary Jane Irwin
    • 2
  1. 1.Department of Computer Science and EngineeringUniversity of South FloridaUSA
  2. 2.Department of Computer Science and EngineeringThe Pennsylvania State UniversityUSA

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