Design Automation for Embedded Systems

, Volume 9, Issue 1, pp 5–18 | Cite as

Optimizing Leakage Energy Consumption in Cache Bitlines

  • Soontae Kim
  • Narayanan Vijaykrishnan
  • Mahmut Kandemir
  • Mary Jane Irwin


As technology scales down into deep-submicron, leakage energy is becoming a dominant source of energy consumption. Leakage energy is generally proportional to the area of a circuit and caches constitute a large portion of the die area. Therefore, there has been much effort to reduce leakage energy in caches. Most techniques have been targeted at cell leakage energy optimization. Bitline leakage energy is critical as well. To this end, we propose a predictive precharging scheme to reduce bitline leakage energy consumption. Results show that energy savings are significant with little performance degradation. Also, our predictive precharging is more beneficial in more aggressively scaled technologies.


leakage energy caches predictive precharging 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Agawa, K., H. Hara, T. Takayanagi, and T. Kuroda. A Bitline Leakage Compensation Scheme for Low-Voltage SRAMS. IEEE Journal of Solid-State Circuits, May 2001.Google Scholar
  2. 2.
    Baron, M. Analog and CPU Wizards Reduce Digital Power: National Semiconductor and ARM Increase Battery Life. Microprocessor Report, vol. 17, Archieve 1, pp. 10–14, 2003.Google Scholar
  3. 3.
    Borkar, S. Design Challenges of Technology Scaling.IEEE Micro, vol. 19, no. 4, 1999.Google Scholar
  4. 4.
    Chandrakasan, A., W. J. Bowhill, and F. Fox. Design of High-Performance Microprocessor Circuits. IEEE Press, 2001.Google Scholar
  5. 5.
    Chen, G., M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. PennBench: A Benchmark Suite for Embedded Java. In Proc. the 5th Annual IEEE Workshop on Workload Characterization, Nov. 2002.Google Scholar
  6. 6.
    Cho, S., P. Yew, and G. Lee. Access Region Locality for High-Bandwidth Processor Memory System Design. In Proc. International Symposium on Microarchitecture, Nov. 1999.Google Scholar
  7. 7.
    Cmelik, B. and D. Keppel. Shade: A Fast Instruction-Set Simulator for Execution Profiling. In Proc. ACM SIGMETRICS Conference on the Measurement and Modeling of Computer Systems, May 1994.Google Scholar
  8. 8.
    Flautner, K., N. S. Kim, S. Martin, D. Blaauw, and T. Mudge. Drowsy Caches: Simple Techniques for Reducing Leakage Power. In Proc. International Symposium on Computer Architecture, July 2002.Google Scholar
  9. 9.
    Hamzaoglu, F. et al. Dual-Vt SRAM Cells with Full-Swing Single-Ended BitLine Sensing for High-oerformance On-Chip Cache in 0.13 μm Technology Generation. In Proc. International Symposium on Low Power Electronics and Design, 2000.Google Scholar
  10. 10.
    Heo, S., K. Barr, M. Hampton, and K. Asanovic. Dynamic Fine-Grain Leakage Reduction UsingLeakage-Biased Bitlines. In Proc. International Symposium on Computer Architecture, May 2002.Google Scholar
  11. 11.
    Inoue, K., T. Ishihara, and K. Murakami. Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption. In Proc. International Symposium on Low Power Electronics and Design, 1999.Google Scholar
  12. 12.
    Kaxiras, S., Z. Hu, and M. Martonosi. Cache Decay: Exploiting Generational Behavior to Reduce Leakage Power. In Proc. International Symposium on Computer Architecture, July 2001.Google Scholar
  13. 13.
    Kim, N. S., K. Flautner, D. Blaauw, and T. Mudge. Drowsy Instruction Caches: Leakage Power Reduction Using Dynamic Voltage Scaling and Cache Sub-Bank Prediction.In Proc. International Symposium on Microarchitecture,2002.Google Scholar
  14. 14.
    Kim, S., N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Predictive Precharging for Bitline Leakage Energy Reduction. In Proc. 15th Annual IEEE International ASIC/SOC Conference, Sept. 2002.Google Scholar
  15. 15.
    Kim, S., N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, and M. J. Irwin. Partitioned Instruction Cache Architecture for Energy Efficiency. ACM Transactions on Embedded Computing Systems, vol. 2, no. 2, 2003.Google Scholar
  16. 16.
    Lee, C., M. Potkonjak, and W. H. Mangione-Smith. Mediabench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. In Proc. International Symposium on Microarchitecture, 1997.Google Scholar
  17. 17.
    Reinman, G. and N. Jouppi. An Integrated Cache Timing and Power Model. Technical Report, Compaq Western Research Lab, 1999.Google Scholar
  18. 18.
    Riggs, R., A. Taivalsaari, and M. Vandenbrink. Programming Wireless Devices with the Java 2 Platform. Addison Wesley, 2001.Google Scholar
  19. 19.
    Santhanam, S., A. J. Baum, et al. A Low-Cost, 300-MHz, RISC CPU with Attached Media Processor. IEEE Journal of Solid-State Circuits, Nov. 1998.Google Scholar
  20. 20.
    Yang, S.-H., M. D. Powel, B. Falsafi, K. Roy, and T. N. Vijaykumar. An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance i-Caches. In Proc. International Symposium onHigh Performance Computer Architecture, Jan. 2001.Google Scholar

Copyright information

© Springer Science + Business Media, Inc. 2004

Authors and Affiliations

  • Soontae Kim
    • 1
  • Narayanan Vijaykrishnan
    • 2
  • Mahmut Kandemir
    • 2
  • Mary Jane Irwin
    • 2
  1. 1.Department of Computer Science and EngineeringUniversity of South FloridaUSA
  2. 2.Department of Computer Science and EngineeringThe Pennsylvania State UniversityUSA

Personalised recommendations