Computational Optimization and Applications

, Volume 48, Issue 1, pp 71–90 | Cite as

A cyclic scheduling problem with an undetermined number of parallel identical processors

Article

Abstract

This paper presents two integer linear programming (ILP) models for cyclic scheduling of tasks with unit/general processing time. Our work is motivated by digital signal processing (DSP) applications on FPGAs (Field-Programmable Gate Arrays)—hardware architectures hosting several sets of identical arithmetic units. These hardware units can be formalized as dedicated sets of parallel identical processors. We propose a method to find an optimal periodic schedule of DSP algorithms on such architectures where the number of available arithmetic units must be determined by the scheduling algorithm with respect to the capacity of the FPGA circuit. The emphasis is put on the efficiency of the ILP models. We show the advantages of our models in comparison with common ILP models on benchmarks and randomly generated instances.

Keywords

Cyclic scheduling Multi-processor scheduling Digital signal processing applications 

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References

  1. 1.
    Bonsma, E., Gerez, S.: A genetic approach to the overlapped scheduling of iterative data-flow graphs for target architectures with communication delays. In: ProRISC Workshop on Circuits, Systems and Signal Processing, 1997 Google Scholar
  2. 2.
    Brucker, P., Kampmeyer, T.: Tabu search algorithms for cyclic machine scheduling problems. J. Sched. 8(4), 303–322 (2005) MATHCrossRefMathSciNetGoogle Scholar
  3. 3.
    Celoxica Ltd.: Platform Developers Kit: Pipelined Floating-point Library Manual (2004). http://www.celoxica.com
  4. 4.
    Dongen, V.H., Gao, G.R.: A polynomial time method for optimal software pipelining. Lect. Not. Comput. Sci. 634, 613–624 (1992) Google Scholar
  5. 5.
    Dupont de Dinechin, B.: Time-indexed formulations and a large neighborhood search for the resource-constrained modulo scheduling problem. In: MISTA’2007, 3rd Multidisciplinary International Scheduling Conference: Theory and Applications, Paris, August 2007 Google Scholar
  6. 6.
    Fan, K., Kublur, M., Park, H., Mahlke, S.: Increasing hardware efficiency with multifunction loop accelerators. In: CODES+ISSS ’06: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis. ACM Press, New York (2006) Google Scholar
  7. 7.
    Fettweis, A.: Wave digital filters: theory and practice. Proc. IEEE 74(2), 270–327 (1986) CrossRefGoogle Scholar
  8. 8.
    Fimmel, D., Müller, J.: Optimal software pipelining under resource constraints. J. Found. Comput. Sci. 12(6) (2001) Google Scholar
  9. 9.
    Franck, B., Neumann, K., Schwindt, C.: Truncated branch-and-bound, schedule-construction, and schedule-improvement procedures for resource-constrained project scheduling. OR Spectr. 23(3), 297–324 (2001) MATHMathSciNetGoogle Scholar
  10. 10.
    Hanen, C.: Study of a np-hard cyclic scheduling problem: The recurrent job-shop. Eur. J. Oper. Res. 72(1), 82–101 (1994) MATHCrossRefGoogle Scholar
  11. 11.
    Hanen, C., Munier, A.: A study of the cyclic scheduling problem on parallel processors. Discrete Appl. Math. 57, 167–192 (1995) MATHCrossRefMathSciNetGoogle Scholar
  12. 12.
    Heemstra, S.M., Gerez, S.H., Herrmann, O.E.: Fast prototyping of datapath-intensive architectures. IEEE Trans. Circuits Syst. I 39(5), 351–364 (1992) MATHCrossRefGoogle Scholar
  13. 13.
    ILOG Inc.: CPLEX Version 9.1 (2005). http://www.ilog.com/products/cplex/
  14. 14.
    Kazuhito, I., Lucke, E., Parhi, K.: ILP based cost-optimal DSP synthesis with module selection and data format conversion. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 6(4) (1999) Google Scholar
  15. 15.
    Kum, K.-I., Sung, W.: Combined word-length optimization and high-level synthesis of digital signal processing systems. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 20(8), 921–930 (2001) CrossRefGoogle Scholar
  16. 16.
    Matoušek, R., Tichý, M., Pohl, A.Z., Kadlec, J., Softley, C.: Logarithmic number system and floating-point arithmetics on FPGA. In: International Conference on Field-Programmable Logic and Applications (FPL ’02), pp. 627–636 (2002) Google Scholar
  17. 17.
    Munier, A.: The complexity of a cyclic scheduling problem with identical machines and precedence constraints. Eur. J. Oper. Res. 91(3), 471–480 (1996) MATHCrossRefGoogle Scholar
  18. 18.
    Paulin, P., Knight, J., Girczyc, E.: Hal: A multi-paradigm approach to automatic data path synthesis. In: 23rd IEEE Design Automation Conf., pp. 263–270, Las Vegas, July 1986 Google Scholar
  19. 19.
    Rabaey, J.M., Chu, C., Hoang, P., Potkonjak, M.: Fast prototyping of datapath-intensive architectures. IEEE Des. Test 8(2), 40–51 (1991) CrossRefGoogle Scholar
  20. 20.
    Rau, B.R., Glaeser, C.D.: Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. In: MICRO 14: Proceedings of the 14th annual workshop on Microprogramming, pp. 183–198, Piscataway, NJ, USA, 1981 Google Scholar
  21. 21.
    Sindorf, S.L., Gerez, S.H.: An integer linear programming approach to the overlapped scheduling of iterative data-flow graphs for target architectures with communication delays. In: PROGRESS 2000 Workshop on Embedded Systems, Utrecht, The Netherlands, 2000 Google Scholar
  22. 22.
    Šůcha, P., Hanzálek, Z.: Deadline constrained cyclic scheduling on pipelined dedicated processors considering multiprocessor tasks and changeover times. Math. Comput. Model. 47(9–10), 925–942 (2008) MATHGoogle Scholar
  23. 23.
    Šůcha, P., Hanzálek, Z., Heřmánek, A., Schier, J.: Scheduling of iterative algorithms with matrix operations for efficient FPGA design–implementation of finite interval constant modulus algorithm. J. VLSI Signal Process. 46(1), 35–53 (2007) CrossRefGoogle Scholar
  24. 24.
    Vesterbacka, M., Palmkvist, K., Sandberg, P., Wanhammar, L.: Implementation of fast dsp algorithms using bit-serial arithmetic. In: National Conference on Electronic Design Automation, Stockholm, March 1994 Google Scholar
  25. 25.
    West, D.B.: Introduction to Graph Theory, 2nd edn. Prentice-Hall, Englewood Cliffs (2001) Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.Department of Control Engineering, Faculty of Electrical EngineeringCzech Technical University in PraguePrague 2Czech Republic
  2. 2.MericaHavlickuv BrodCzech Republic

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