Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates

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Abstract

Lessening power consumption during the test and reducing test time are the main goals of this paper. The power consumption is a major problem of movable equipment which needs large working time and minimum charging time. Power consumption has become significant in handheld communication structures and battery functioned gadgets such as laptops, mobile phones, pacemakers, multimedia goods and cellular phones. Reducing the power consumption is very important scenario which is becoming popular in the electronics industry for test power reduction and one of the popular interesting areas of research insights. The scan chains are long connected chain of flip flops normally made to simplify the testing and monitoring test of the circuit by allowing the user to shift out the scan in data and produce new values for comparison. The scan chain architecture is designed using a chain of flip-flops. These flip-flops are made design for testability by introducing a multiplexer before the input terminal. The multiplexer chooses single input, may be the normal input bit or the test mode bit. The circuit is designed in order to reduce the average power consumed by the circuit. The circuit is designed using Altera Quartus II Tool and the outputs were analyzed. The circuit is analyzed for various working conditions and also for various factors which affects the testing time and the testing power.

Keywords

Design for testability (DFT) Built in self test (BIST) Scan chain Low power logic CMOS Transmission gates 

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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of ECESNS College of TechnologyCoimbatoreIndia
  2. 2.Department of EEESNS College of TechnologyCoimbatoreIndia

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