Cluster Computing

, Volume 22, Supplement 6, pp 13773–13783 | Cite as

Systolic array multiplier for augmenting data center networks communication link

  • S. SubathradeviEmail author
  • C. Vennila


The paper will present a heuristic architecture that is used for the systolic array multiplier for the delay and power—the delay product minimization using various input bit sizes. Systolic architecture maps high-level computation into hardware structures. As these have regularity and can be easily reckoned, the systolic systems are easy to implement. This architecture results in cost effective, better performance and special purpose systems that can solve a wide variety of problems. An effective method for designing Very Large Scale Integration (VLSI) architecture that is based on the proper decomposition technique that uses circular correlations has been presented. Here the multiplication is a commonly used operation in both Mathematics and also in Digital Signal Processing applications. The Systolic algorithm will be an efficient algorithm that performs binary multiplication and the Systolic architectures will provide better performance in design like that of the multiplier, matrix multiplication, the Finite Impulse Response based filter and also the Distributed Array Arithmetic. This work proposed a VLSI architecture based on systolic multiplier that can be implemented on Network links to reduce energy consumption. The proposed work concentrate on the development of a novel architecture having decomposition cells used for the systolic multiplier. There are two different architectures that are proposed and among them the Architecture-I has been designed having the decomposition cells along with registers in case of the feed forward path delay for the delay minimization. This proposed work has resulted in the delay reduction of about 32% that is compared to the existing work. In the architecture-II and their Processing Elements that have been designed along with the tristate buffers and also the multiplexer that is based on the full adder in power minimization. Their results in a lower power delay based product of about 6% compared to the current work and the Field Programmable Gate Array tested proved the delay and the improvement of power-delay product compared to other conventional architectures.


VLSI Systolic multiplier Decomposition cells Data path delay Pipelining and reconfiguration 


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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Anna University –BIT CampusTiruchirappalliIndia
  2. 2.Saranathan College of EngineeringTiruchirappalliIndia

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