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Cluster Computing

, Volume 22, Supplement 6, pp 13773–13783 | Cite as

Systolic array multiplier for augmenting data center networks communication link

  • S. SubathradeviEmail author
  • C. Vennila
Article
  • 52 Downloads

Abstract

The paper will present a heuristic architecture that is used for the systolic array multiplier for the delay and power—the delay product minimization using various input bit sizes. Systolic architecture maps high-level computation into hardware structures. As these have regularity and can be easily reckoned, the systolic systems are easy to implement. This architecture results in cost effective, better performance and special purpose systems that can solve a wide variety of problems. An effective method for designing Very Large Scale Integration (VLSI) architecture that is based on the proper decomposition technique that uses circular correlations has been presented. Here the multiplication is a commonly used operation in both Mathematics and also in Digital Signal Processing applications. The Systolic algorithm will be an efficient algorithm that performs binary multiplication and the Systolic architectures will provide better performance in design like that of the multiplier, matrix multiplication, the Finite Impulse Response based filter and also the Distributed Array Arithmetic. This work proposed a VLSI architecture based on systolic multiplier that can be implemented on Network links to reduce energy consumption. The proposed work concentrate on the development of a novel architecture having decomposition cells used for the systolic multiplier. There are two different architectures that are proposed and among them the Architecture-I has been designed having the decomposition cells along with registers in case of the feed forward path delay for the delay minimization. This proposed work has resulted in the delay reduction of about 32% that is compared to the existing work. In the architecture-II and their Processing Elements that have been designed along with the tristate buffers and also the multiplexer that is based on the full adder in power minimization. Their results in a lower power delay based product of about 6% compared to the current work and the Field Programmable Gate Array tested proved the delay and the improvement of power-delay product compared to other conventional architectures.

Keywords

VLSI Systolic multiplier Decomposition cells Data path delay Pipelining and reconfiguration 

References

  1. 1.
    Smith, M.J.S.: Application Specific Integrated Circuits, 3rd edn. Pearson Education Inc, Reading, MA (2006)Google Scholar
  2. 2.
    Parhi, K.K.: VLSI digital signal processing systems design and implementation, 2nd edn. Weily, New York (1999)Google Scholar
  3. 3.
    Uyemura, J.P.: Introduction to VLSI Circuits and Systems. Wiley, New York (2012)Google Scholar
  4. 4.
    Ramkumar, B., Sreedeep, V., Kittur, H.M.: A design technique for faster Dadda multiplier. IEEE Member (2011)Google Scholar
  5. 5.
    Sinha, B.P., Srimani, P.K.: Fast parallel algorithms for binary multiplication and their implementation on systolic architectures. IEEE Trans. Comput. 38(3), 424–431 (1989)MathSciNetCrossRefGoogle Scholar
  6. 6.
    Uyemmura: Digitla Circuits, 2nd edn. Prentice Hall, Upper Saddle River (1998)Google Scholar
  7. 7.
    Azadfar, M.M.: Implementation of a optimized systolic array architecture for FSBMA using FPGA for real-time applications. Int. J. Comput. Sci. Netw. Secur. 8(3), 46–51 (2008)Google Scholar
  8. 8.
    Qasim, S.M., Abbasi, S.A., Almashary, B.: A proposed FPGA-based parallel architecture for matrix multiplication. In: IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 1763–1766 (2008)Google Scholar
  9. 9.
    Kung, H.T.: why systolic architecture? IEEE Comput. 15(1), 37–46 (1982)CrossRefGoogle Scholar
  10. 10.
    Sidhu, H.H.S.: Design and implementation modified booth algorithm and systolic multiplier using FPGA. Int. J. Eng. Res. Technol. (IJERT) 2(11) (2013)Google Scholar
  11. 11.
    Johnson, K.T., Hurson, A.R.: General Purpose Systolic Arrays. Pennsylvania State University, State College (1993)CrossRefGoogle Scholar
  12. 12.
    Perin, G., Mesquita, D.G., Martins, J.B.: Montgomery modular multiplication on reconfigurable hardware: systolic versus multiplexed implementation. Int. J. Reconfig. Comput. 2, 230–240 (2011).  https://doi.org/10.1155/2011/127147 CrossRefGoogle Scholar
  13. 13.
    Kung, S.Y.: VLSI Array Processors, 2nd edn. Prentice-Hall, Upper Saddle River (1988)Google Scholar
  14. 14.
    Kung, H.T.: Why systolic architectures? IEEE Commun. Syst. 15, 341–349 (1989)Google Scholar
  15. 15.
    Kung, H.T.: Why systolic architectures? IEEE Comput. 15, 23–31 (1982)CrossRefGoogle Scholar
  16. 16.
    Kung, H.T., Lo, S.C., Lewis, P.A.: Optimal systolic design for the transitive closure and the shortest path problems. IEEE Tans. Comput. C-36, 603–614 (1987)CrossRefGoogle Scholar
  17. 17.
    Smith, R., Sobelman, G.: Simulation-based design of programmable systolic arrays. Comput. Aided Des. 2(6), 669–675 (1901)zbMATHGoogle Scholar
  18. 18.
    Kumar, A.: Fundamentals of Digital Circuits, 2nd edn. Prentice Hall, India Publication, New Delhi (2003)Google Scholar
  19. 19.
    Agrawal, E.: Systolic and semisystolic multiplier. Int. J. Electron. Commun. Eng. 3(2), 90–93 (2013)Google Scholar
  20. 20.
    Sruthikeerthana, V., Pavithra, S.: Design of the add multiply operator using modified booth recorder. Int. J. Sci. Res. 5(3), 43–55 (2016)Google Scholar
  21. 21.
    Arechabala, J., Boemo, E.I., Meneses, J., Moreno, F., Barrio, L.: Full systolic binary multiplier. IEEE Proc G 139(2), 312–321 (1992)Google Scholar
  22. 22.
    Singh, K.D., Jyothi, K.: Design and implementation of VLSI 8-bit systolic array multiplier. Int. J. Adv. Res. Electr. Electron. Instrum. Eng. 3(11), 241–249 (2014)Google Scholar
  23. 23.
    Langade, P.H., Patil, S.B.: A survey on systolic array multiplier and its implementation on FPGA. Int. J. Adv. Res. Electron. Commun. Eng. (IJARECE) 4(5), 124–131 (2015)Google Scholar
  24. 24.
    Subathradevi, S., Vennila, C.: Modified architecture for binary array multiplier with reduced delay using tristate buffers. Indian J. Sci. Technol. 8(23), 1–4 (2015)CrossRefGoogle Scholar
  25. 25.
    Krishna, K.G., Santhosh, B., Sridhar, V.: Design of wallace tree multiplier using compressors. Int. J. Eng. Sci. Res. Technol. 2(9), 102–110 (2013)Google Scholar
  26. 26.
    Saptalakar, B.K., Kale, D., Rachannvar, M., Pavankumar, M.K.: Design and implementation of VLSI systolic array multiplier for DSP applications. Int. J. Sci. Eng. Technol. 2(3), 156–167 (2013)Google Scholar
  27. 27.
    Kumar, K.G., Prasannam, J. D., Christy, M.A.: Analysis of low power, area and high speed multipliers for DSP applications. Int. J. Emerg. Technol. Adv. Eng. 4(3) (2014)Google Scholar
  28. 28.
    Mathe, S.E., Boppana, L.: Low-power and low-hardware bit-parallel polynomial basis systolic multiplier over GF (2m) for irreducible polynomials. ETRI J. 39(4), 570–581 (2017)CrossRefGoogle Scholar
  29. 29.
    Langade, P.H., Patil, S.B.: Design of improved systolic array multiplier and its implementation on FPGA. Int. J. Eng. Res. General Sci. 3(6), 830–838 (2015)Google Scholar
  30. 30.
    Jain, A.K.: A sinusoidal family of unitary transforms. IEEE Trans. Pattern Mach. Intell. 1, 356–365 (1979)CrossRefGoogle Scholar
  31. 31.
    Stine, J.E.: Digital Computer Arithmetic Data Path Design Using Verilog HDL, 2nd edn. Weily, New York (1999)Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Anna University –BIT CampusTiruchirappalliIndia
  2. 2.Saranathan College of EngineeringTiruchirappalliIndia

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