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Cluster Computing

, Volume 22, Supplement 3, pp 6907–6912 | Cite as

Designing low power magentic flip flop in 45 nm FDSOI technology for large scale cluster based engineering application

  • K. SakthimuruganEmail author
  • K. Geetha
Article
  • 64 Downloads

Abstract

An enhanced nonvolatile magnetic flip-flop is introduced in this paper. Spin torque transfer magnetic tunnel junction (MTJ) with the breakdown concept is used to design FDSOI circuit, which is implemented with 45 nm. The proposed flip-flop structure named enhanced nonvolatile magnetic flip-flop which uses the power retention technique in order to control the leakage power Large Scale Cluster based Engineering Application. The proposed design requires less design effort and offers greater power reduction up to 75 % and smaller area cost than the existing method.

Keywords

Non volatile flip-flop Magnetic tunneling junction Leakage power control 45 nm FD-SOI technology 

References

  1. 1.
    Kao, J.T., Chandrakasan, A.P.: Dual-threshold voltage techniques for low-power digital circuits. IEEE J. Solid-State Circuits 35(7), 1009–1018 (2000)CrossRefGoogle Scholar
  2. 2.
    Narendra, S., Keshavarzi, A., Bloechel, B.A., Borkar, S., De, V.: Forward body bias for microprocessors in 130-nm technology generation and beyond. IEEE J. Solid-State Circuits 38, 696–701 (2003)CrossRefGoogle Scholar
  3. 3.
    Lackey, D.E. et al.: Managing power and performance for system-onchip designs using voltage islands. In: IEEE/ACM International Conference on Computer Aided Design, ICCAD 2002, pp. 195–202, 10–14 November, 2002Google Scholar
  4. 4.
    Srinivasulu, P., Rao, K.S., Babu, B.A.: Low power design techniques for CMOS circuits & systems. Int. J. Recent Trends Eng. Technol. 4(4) (2010)Google Scholar
  5. 5.
    Subramanyan, B.D., Nunnez, A.: Analysis of sub threshold leakage reduction in CMOS digital circuits. In: Proceedings of the 13th NASA VLSI Symposium, June, pp. 5–6 (2007)Google Scholar
  6. 6.
    Aswath, A.R., Puttaaraju, M., Kalpana, A.B.: An implementations of integral low power techniques for modern cell-based VLSI designs. Int. J. Comput. Electr. Eng. 3(3), 394 (2011)CrossRefGoogle Scholar
  7. 7.
    Karimi, G., Alimoradi, A.: Multi-purpose technique to decrease leakage power in VLSI circuits. Can. J. Electric. Electron. Eng. 2(3), 71–74 (2011)Google Scholar
  8. 8.
    Priya, M.G, Baskaran, K., Krishnaveni, D.: A novel leakage power reduction technique for CMOS VLSI circuits. Int. J. Appl. Eng. Res. 2(2) (2011)Google Scholar
  9. 9.
    Hu, C.: Device and technology impact on low power electronics. Low Power Design Methodologies, pp. 21–36. Kluwer Academic, Boston (1996)CrossRefGoogle Scholar
  10. 10.
    Rabaey, J.: Digital Integrated Circuits: A Design Perspective. Wesley, Reading, MA (1993)Google Scholar
  11. 11.
    Alam, M.A., Weir, B.E., Silverman, P.J.: A study of soft and hard breakdown—Part I: analysis of statistical percolation conductance. In: IEEE Transactions on Electron Devices, vol. 49, No. 2 (2002)CrossRefGoogle Scholar
  12. 12.
    Kuhnt, Sonja: Breakdown concepts for contingency tables. Springer, Upper Saddle River (2009)zbMATHGoogle Scholar
  13. 13.
    Cai, H., Wang, Y., de Barros Naviner, L.A., Zhao, W.: Breakdown analysis of magnetic flip-flop with 28nm UTBB FDSOI technology. In: IEEE Transactions on Device and Materials Reliability (2016)Google Scholar
  14. 14.
    Nanoti, N.G., Gawande, P.D.: Design approach towards high performance memory of 6 transistors SRAM cell using 45nm CMOS technology. Int J Innov Res Electr. Electron. Instrum. Control Eng. 2(2) (2014)Google Scholar
  15. 15.
    Gupta, I., Arora, N., Singh, B.P.: Analysis of several 2:1 multiplexer circuits at 90nm and 45nm technologies. Int. J. Sci. Res. Publ. 2(2), February 2012 ISSN 2250-3153Google Scholar
  16. 16.
    Ramani, G., Geetha, K.: An efficient code compression for MIPS32 processor using dictionary and bit-mask based static and dynamic frequency algorithm & COMPEL. Int. J. Comput. Math. Electr. Electron. Eng. 35(5) (2016)Google Scholar
  17. 17.
    Sangeetha, B., Geetha, K.: Performance evaluation of conventional and intelligent controller based shunt active filter. IET Digital Library (2013)Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.S. Veerasamy Chettiar College of Engineering and TechnologyTirunelveliIndia
  2. 2.Department of ECEKarpagam Institute of TechnologyCoimbatoreIndia

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