Advertisement

All-digital 1-1 MASH delta-sigma time-to-digital converter via time-mode signal processing

  • Young Jun Park
  • Fei YuanEmail author
Article
  • 10 Downloads

Abstract

This paper presents an all-digital 1-1 MASH \(\Delta \Sigma\) time-to-digital converter (TDC) using time-mode signal processing. A cascode time adder with a raised inverter threshold voltage is proposed to minimize the deterministic timing error caused by the current mismatch of the discharge paths of the time adder. A differential time integrator consisting of a pair of identical single-ended time integrators is proposed to minimize the effect of the nonlinearities of the single-ended time integrator. The random and deterministic timing errors of the TDC are analyzed. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results demonstrate that the TDC exhibits 40 dB per decade noise-shaping at high frequencies. The cascode-configured discharge paths and raised threshold voltage of the load inverter improve the linearity of the TDC. The TDC achieves 1.9 ps time resolution over 48–415 kHz signal band while consuming 502 μW.

Keywords

CMOS time-mode circuits Delta-sigma time-to-digital converters Time adders Time registers Time integrators 

Notes

Acknowledgements

Financial support from Natural Science and Engineering Research Council of Canada, and computer-aided design tools from CMC Microsystems, Kingston, ON, Canada are gratefully acknowledged.

References

  1. 1.
    Yoshiaki, T., & Takeshi, A. (1971). Simple voltage-to-time converter with high linearity. IEEE Transactions on Instrumentation and Measurement, 20(2), 120–122.Google Scholar
  2. 2.
    Porat, D. (1973). Review of sub-nanosecond time-interval measurements. IEEE Transactions on Nuclear Science, 20, 36–51.CrossRefGoogle Scholar
  3. 3.
    Li, G., Tousi, Y., Hassibi, A., & Afshari, E. (2009). Delay-line-based analog-to-digital converters. IEEE Transactions on Circuits and Systems II, 56(6), 464–468.CrossRefGoogle Scholar
  4. 4.
    Straayer, M., & Perrott, M. (2008). A 12-bit, 10-MHz bandwidth, continuous-time \(\Delta \Sigma\) ADC with a 5-bit, 950-MS/s VCO-based quantizer. IEEE Journal of Solid-State Circuits, 43(4), 805–814.CrossRefGoogle Scholar
  5. 5.
    Park, M., & Perrott, M. (2009). A single-slope 80 Ms/s ADC using two-step time-to-digital conversion. In IEEE international symposium on circuits and systems (pp. 1125–1128).Google Scholar
  6. 6.
    Jang, T. K., Kim, J., Yoon, Y. G., & Cho, S. (2012). A highly-digital VCO-based analog-to-digital converter using phase interpolator and digital calibration. IEEE Transactions on VLSI Systems, 20(8), 1368–1372.CrossRefGoogle Scholar
  7. 7.
    Yu, W., Kim, J., Kim, K., & Cho, S. (2013). A time-domain high-order MASH \(\Delta \Sigma\) ADC using voltage-controlled gated-ring oscillator. IEEE Transactions on Circuits and Systems I, 60(4), 856–866.CrossRefGoogle Scholar
  8. 8.
    Yu, W., Kim, K., & Cho, S. (2014). A 148 \(fs_{rms}\) integrated noise 4 MHz bandwidth second-order \({\Delta \Sigma }\) time-to-digital converter with gated switched-ring oscillator. IEEE Transactions on Circuits and Systems I, 61(8), 2281–2289.CrossRefGoogle Scholar
  9. 9.
    Kim, J., Kim, Y., Kim, K., Yu, W., & Cho, S. (2015). A hybrid-domain two-step time-to-digital converter using a switch-based time-to-voltage converter and SAR ADC. IEEE Transactions on Circuits and Systems II, 62, 631–635.CrossRefGoogle Scholar
  10. 10.
    Tokairin, T., Okada, M., Kitsunezuka, M., Maeda, T., & Fukaishi, M. (2010). A 2.1-to-2.8-GHz low-phase-noise all-digital frequency synthesizer with a time-windowed time-to-digital converter. IEEE Journal of Solid-State Circuits, 45(12), 2582–2590.CrossRefGoogle Scholar
  11. 11.
    Hong, J., Kim, S., Liu, J., Xing, N., Jang, T., Park, J., Kim, J., Kim, T., & Park, H. (2012). A 0.004 mm2 250 μW \(\Delta \Sigma\) TDC with time-difference accumulator and a \(0.012 \text{mm }^{2}\,2.5 \text{mW }\) bang–bang digital PLL using PRNG for low-power SoC applications. In IEEE international solid-state circuits conference, digest of technical papers (pp. 240–242).Google Scholar
  12. 12.
    Henzler, S. (2010). Time-to-digital converters. New York: Springer.CrossRefGoogle Scholar
  13. 13.
    Straayer, M., & Perrott, M. (2009). A multi-path gated ring oscillator TDC with first-order noise shaping. IEEE Journal of Solid-State Circuits, 44(4), 1089–1098.CrossRefGoogle Scholar
  14. 14.
    Konishi, T., Okumo, K., Izumi, S., Yoshimoto, M., & Kawaguchi, H. (2012). A 61 dB SNDR 700 μm second-order all-digital TDC with low-jitter frequency shift oscillator and dynamic flipflops. In Symposium on VLSI circuits, digest of technical papers (pp. 190–191).Google Scholar
  15. 15.
    Cao, T., Wisland, D., & Lande, T. (2012). High resolution frequency-based delta-sigma modulator utilizing multi-phase quantizer. In Proceedings of the IEEE international symposium on circuits and systems (pp. 3009–3012).Google Scholar
  16. 16.
    Daniels, J., Dehaene, W., Steyaert, M., & Wiesbauer, A. (2010). A \(0.02\,\text{mm }^{2}\) 65 nm CMOS 30 MHz BW all-digital differential VCO-based ADC with 64dB SNDR. In Symposium on VLSI circuits, digest of technical papers (pp. 155–156).Google Scholar
  17. 17.
    Si, R., Li, F., & Zhang, C. (2012). A 100 MH/s, 7 bit VCO-based ADC which is used in time interleaved ADC architecture. In Proceedings of the international conference on consumer electronics, communications and networks (pp. 4–7).Google Scholar
  18. 18.
    Abdulaziz, M., Tormanen, M., & Sjoland, H. (2014). A compensation technique for two-stage differential OTAs. IEEE Transactions on Circuits and Systems II, 61(8), 594–598.CrossRefGoogle Scholar
  19. 19.
    Akbari, M., & Hashemipour, O. (2014). Enhancing transconductance of ultra-low-power two-stage folded cascode OTA. Electronics Letters, 50(21), 1514–1516.CrossRefGoogle Scholar
  20. 20.
    Gray, P., Hust, P., Lewis, S., & Meyer, R. (2001). Analysis and design of analog integrated circuits (4th ed.). New York: Wiley.Google Scholar
  21. 21.
    Razavi, B. (2001). Design of analog CMOS integrated circuits. Boston: McGraw-Hill.Google Scholar
  22. 22.
    Gande, M., Maghari, N., Oh, T., & Moon, U. (2012). A 71 dB dynamic range third-order \(\Delta \Sigma\) TDC using charge pump. In Symposium on VLSI circuits, digest of technical papers (pp. 168–169).Google Scholar
  23. 23.
    Kwon, C., Kim, H., Park, J., & Kim, S. (2016). A 0.4-mw, 4.7-ps resolution single-loop \(\Delta \Sigma\) TDC using a half-delay time integrator. IEEE Transactions on VLSI Systems, 24(3), 1184–1188.CrossRefGoogle Scholar
  24. 24.
    Ali-Bakhshian, M., & Roberts, G. (2012). A digital implementation of a dual-path time-to-time integrator. IEEE Transactions on Circuits and Systems I, 59(11), 2578–2591.MathSciNetCrossRefGoogle Scholar
  25. 25.
    Abdelfattah, M., Roberts, G., & Chodavarapu, V. (2014). All-digital time-mode elliptic filters based on the operational simulation of LC ladders. In Proceedings of the international symposium on circuits and systems (pp. 2125–2128).Google Scholar
  26. 26.
    Abdelfattah, M., & Roberts, G. (2016). Experimental operation of time-mode building blocks using a time-mode switched-delay unit. In Proceedings of the IEEE midwest symposium on circuits and systems (pp. 1–4).Google Scholar
  27. 27.
    Kim, S. (2010). Time domain algebraic operation circuits for high performance mixed-mode system. MS thesis, Korean Advanced Institute of Science and Technology.Google Scholar
  28. 28.
    Park, Y., Amor, D., & Yuan, F. (2016). Time integrator for mixed-mode signal processing. In Proceedings of the IEEE international symposium on circuits and systems (pp. 826–829).Google Scholar
  29. 29.
    Yuan, F., & Khan, G. (2017). All-digital gated ring oscillator delta-sigma modulators. Analog Integrated Circuits and Signal Processing, 92(3), 483–488.CrossRefGoogle Scholar
  30. 30.
    Park, Y., & Yuan, F. (2017). 1–1 MASH delta-sigma time-to-digital converter with differential cascode time integrator. In IEEE midwest symposium on circuits and systems (pp. 1005–1008).Google Scholar
  31. 31.
    Rabaey, J. M., Chandrakasan, A., & Nikolic, B. (2003). Digital integration circuits: A design perspective. Englewood Cliffs, NJ: Prentice-Hall.Google Scholar
  32. 32.
    Taillefer, C., & Roberts, G. (2009). Delta-sigma A/D converter via time-mode signal processing. IEEE Transactions on Circuits and Systems I, 56(9), 1908–1920.MathSciNetCrossRefGoogle Scholar
  33. 33.
    Straayer, M., & Perrott, M. Z. (2008). An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC. In IEEE symposium on VLSI circuits (pp. 82–83).Google Scholar
  34. 34.
    Cao, Y., Leroux, P., Cock, W. D., & Steyaert, M. (2011). A 1.7 mW 11b 1–1–1 MASH \(\Delta \Sigma\) time-to-digital converter. In IEEE international solid-state circuits conference, digest of technical papers (pp. 480–481).Google Scholar
  35. 35.
    Wu, Y., Lu, P., & Staszewski, R. (2015). A 103 fsrms 1.32 mW 50 MS/s 1.25 MHz bandwidth two-step flash-\(\Delta \Sigma\) time-to-digital converter for ADPLL. In Proceedings of the IEEE RFIC (pp. 95–98).Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Electrical, Computer, and Biomedical EngineeringRyerson UniversityTorontoCanada
  2. 2.TSMC Design Technology Canada Inc.KanataCanada

Personalised recommendations