Low-light-level CMOS imaging sensor with CTIA and digital correlated double sampling
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This paper presents two low-light-level CMOS image sensors with capacitive transimpedance amplifier (CTIA) and digital correlated double sampling (CDS). In order to achieve high sensitivity for low-light-level CMOS image sensor, the CTIA pixel circuit with a small integration capacitor is used. In order to remove the noise of the low-light-level CMOS image sensor, a digital CDS is designed, which realizes the subtraction algorithm between the reset signal and pixel signal off-chip. The pixel reset noise, pixel fixed-pattern noise (FPN) and the column FPN can be greatly reduced by this digital CDS. Two test chips based on this method with 256 × 256 pixel array are fabricated in a 0.35 μm CMOS technology, one is based on DC-coupled CTIA pixel circuit, and the other one is based on AC-coupled CTIA pixel circuit. These two chips are designed with the same column sigma-delta analog-to-digital (∑∆ ADC), whose resolution is 15-bit. At a frame rate of 7 fps, the low-light-level CMOS image sensor with DC-coupled CTIA pixel circuit and digital CDS can capture recognizable images with the illumination down to 0.05 lux. The low-light-level CMOS image sensor with AC-coupled CTIA pixel circuit can reduce the dark current by reducing the reverse bias voltage of the photodiode.
KeywordsCMOS image sensor Digital correlated double sampling (digital CDS) Low-light-level Capacitive transimpedance amplifier (CTIA)
The authors wish to thank Jizhongshun, Chenshaolin for FPGA test code implementation.
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