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Analog Integrated Circuits and Signal Processing

, Volume 101, Issue 3, pp 601–609 | Cite as

A modified Dickson’s charge pump circuit with high output voltage and high pumping efficiency

  • Liang ZhangEmail author
  • Xu Cheng
  • Xianjin Deng
Article
  • 62 Downloads

Abstract

A modified Dickson’s charge pump circuit with high output voltage and high pumping efficiency fabricated by IHP’s 130 nm SiGe BiCMOS process is proposed. Instead of traditional on-chip metal–insulator–metal capacitor, a modified vertical parallel plate capacitor is utilized as the pumping capacitor, which owns a breakdown voltage higher than 84 V and an improved capacitance density of 1.92 fF/μm2. Thus, the output voltage and chip size of charge pump circuit are not limited by the pumping capacitor. To further improve the voltage pumping efficiency and make the circuit suitable for low voltage operation, the threshold voltage and the body effect coefficient is eliminated by using a dynamic control to both the charge transfer switches and the MOSFETs body voltages. Simulated result of a 35-stage charge pump circuit with an output voltage higher than 100 V is demonstrated. A 7-stage charge pump circuit with an output voltage of 13.8 V and a pumping efficiency of 75%, higher than the traditional Dickson’s charge pump circuits, is fabricated and measured.

Keywords

Charge pump circuit Dynamic control High output voltage High pumping efficiency Vertical parallel plate (VPP) capacitor 

Notes

References

  1. 1.
    Mahmoud, A., Alhawari, M., Mohammad, B., Saleh, H., & Ismail, M. (2019). A gain-controlled, low-leakage Dickson charge pump for energy-harvesting applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,27, 1–10.CrossRefGoogle Scholar
  2. 2.
    Peng, H., Tang, N., Yang, Y., & Heo, D. (2014). CMOS startup charge pump with body bias and backward control for energy harvesting step-up converters. IEEE Transactions on Circuits and Systems I: Regular Papers,61(6), 1618–1628.CrossRefGoogle Scholar
  3. 3.
    Dickson, J. F. (1976). On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique. IEEE Journal of Solid-State Circuits,11(3), 374–378.CrossRefGoogle Scholar
  4. 4.
    Tsai, J. H., Ko, S. A., Wang, C. W., Yen, Y. C., Wang, H. H., Huang, P. C., et al. (2015). A 1 v input, 3 v-to-6 v output, 58%-efficient integrated charge pump with a hybrid topology for area reduction and an improved efficiency by using parasitics. IEEE Journal of Solid-State Circuits,50(11), 2533–2548.CrossRefGoogle Scholar
  5. 5.
    Huang, Y. C., Ker, M. D., & Lin, C. Y. (2012). Design of negative high voltage generator for biphasic stimulator with SoC integration consideration. In Proceedings of IEEE Bio-CAS (pp. 1–4).Google Scholar
  6. 6.
    Wu, J. T., & Chang, K. L. (1998). MOS charge pumps for low voltage operation. IEEE Journal of Solid-State Circuits,33(4), 592–597.CrossRefGoogle Scholar
  7. 7.
    Wang, X., Wu, D., Qiao, F., Zhu, P., Li, K., Pan, L., et al. (2009). A high efficiency CMOS charge pump for low voltage operation. In IEEE international conference on asic (pp. 320–323).Google Scholar
  8. 8.
    Shin, J., Chung, I. Y., Park, Y. J., & Min, H. S. (2000). A new charge pump without degradation in threshold voltage due to body effect. IEEE Journal of Solid-State Circuits,35(8), 1227–1230.CrossRefGoogle Scholar
  9. 9.
    Ker, M. D., Chen, S. L., & Tsai, C. S. (2006). Design of charge pump circuit with consideration of gate-oxide reliability in low voltage CMOS processes. IEEE Journal of Solid-State Circuits,41(5), 1100–1107.CrossRefGoogle Scholar
  10. 10.
    Kim, J. Y., Park, S. J., Kwon, K. W., Kong, B. S., Choi, J. S., & Jun, Y. H. (2014). Cmos charge pump with no reversion loss and enhanced drivability. IEEE Transactions on Very Large Scale Integration Systems,22(6), 1441–1445.CrossRefGoogle Scholar
  11. 11.
    Yu, X., Moez, K., Wey, I. C., Sawan, M., & Chen, J. (2016). A fully-integrated multistage cross-coupled voltage multiplier with no reversion power loss in standard cmos process. IEEE Transactions on Circuits and Systems II: Express Briefs,99, 1.Google Scholar
  12. 12.
    Emira, A., Abdelghany, M., Elsayed, M., Elshurafa, A. M., Sedky, S., & Salama, K. N. (2013). All-pmos 50-v charge pumps using low-voltage capacitors. IEEE Transactions on Industrial Electronics,60(10), 4683–4693.CrossRefGoogle Scholar
  13. 13.
    Kim, J., Plouchart, J. O., Zamdmer, N., & Sherony, M. (2003). 3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits. In 2003 Symposium on VLSI circuits, 2003. Digest of technical papers. (pp. 29–32). IEEE.Google Scholar
  14. 14.
    Aparicio, R., & Hajimiri, A. (2002). Capacity limits and matching properties of integrated capacitors. IEEE Journal of Solid-State Circuits,37(3), 384–393.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Microsystem and Terahertz Research CenterChina Academy of Engineering PhysicsChengduChina
  2. 2.Institute of Electronic EngineeringChina Academy of Engineering PhysicsMianyangChina

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