Low power CMOS variable gain amplifier design for a multistandard receiver WLAN/WIMAX/LTE
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This paper deals with a new compact low-power variable gain amplifier (VGA) architecture design for wireless communication multistandard receivers. The proposed VGA is a two stages cascaded topology that includes a folded cascode operational transconductance amplifier stage and a VGA core. The new “cell” structure has been introduced to demonstrate the performance enhancement with the use of only one VGA stage. The heuristic method is used to optimize the proposed circuit performance for high gain, low noise and low power consumption. This circuit is implemented and simulated using device-level description of TSMC 0.18 µm CMOS process. The simulation results indicate that the new VGA achieves a gain ranging from a minimum of − 25 dB toa maximum reaching 79 dB with a large bandwidth of 200 MHz. The designed VGA circuit acquires a noise figure less than 18 dB, an input referred noise of around 9.3 nV2/Hz and the third order intercept point measured at the input (IIP3) of 15 dBm. The proposed circuit consumes only 0.5 mW under 1.8 V supply voltage.
KeywordsVGA cell FC OTA Multistandard receiver Optimization heuristic High gain Low power consumption
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