A 96.88% area-saving and 99.72% energy-reduction switching scheme for SAR ADC with a novel two-step quantisation technique
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This paper presents a novel area-saving and energy-efficient switching capacitor structure for successive approximation register analog-to-digital conversions, which uses a two-step quantisation logic control switching scheme. The two steps are coarse and fine quantisation respectively. During the coarse quantisation, there is no power consumption at the first two cycles. The fine quantisation does not increase the number of binary capacitors while consumes no energy. Therefore, the two-step quantisation switching scheme can significantly reduce both the power consumption and the capacitor area. Simulation results show that the structure can reduce the average energy and the capacitor area by 99.72% and 96.88% respectively over the conventional method.
KeywordsSAR ADC Switching scheme Energy-efficient Area-saving Single-sided switching Two-step quantisation Monotonic
This work was supported by the National Natural Science Foundation of China (Nos. 61625403, 61874174, 61674118, 61874173, 61804110).
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