A low energy switching scheme for SAR ADC with MSB-splitting DAC structure
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A high energy-efficiency tri-level switching scheme for successive approximation register converters (SAR ADCs) is presented. The most significant bit-splitting digital to analogue converter and the least significant bit-down technique are combined in this work. The proposed scheme achieves 99.76% saving in switching energy and 75% area reduction compared with the traditional scheme. Besides large switching energy saving, the common mode voltage keeps constant except the LSB conversion, which reduces the dynamic offset of the comparator.
KeywordsSAR ADC Switching scheme MSB-splitting capacitor LSB-down technique
This work was supported by the Fundamental Research Funds for the Central Universities under the Project Number of 2242018K30006.
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