A novel capacitor switching scheme for successive approximation register analogue-to-digital converters is proposed which can achieve a high energy saving, with only two references, Vref and gnd. Due to the two-step architecture is adopted here, the total capacitance is reduced by 48.44% over the conventional structure. Furthermore, based on the most-significant bit capacitor using split-capacitor procedure and monotonic switching method, the proposed switching scheme achieves 99.74% less switching energy over the conventional architecture. Note that during the design procedure, the complexity of logic and auxiliary power supply circuits are further reduced by the lack of the common voltage (Vcm). Besides the significant energy saving in the switching process, the proposed capacitor architecture also has zero consumption in reset energy. Matlab simulation results show the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.644 LSB and 0.825 LSB.
SAR ADC Reference-free Energy-efficiency Area-saving Switching scheme
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This work was supported by the National Natural Science Foundation of China (Nos. 61674118, 61625403, 61874174, 61874173), National Science and Technology Major Project of China (No. 2016ZX03002007), the Science and Technology Fund of Zhejiang Province under Grant 2015C31090.
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