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A PVT compensated nano-ampere current reference in 0.18 µm CMOS

  • R. SanjayEmail author
  • K. Hemanth Kumar
  • B. Venkataramani
Mixed Signal Letter
  • 15 Downloads

Abstract

A PVT compensated sub-µA current reference is proposed in this paper. It is based on the summation of a proportional to absolute temperature (PTAT) current with a complementary to absolute temperature current. The current generators are realized using the subthreshold beta multipliers. The PTAT current generator of the proposed current reference behaves always as PTAT independent of transistor sizing. The process compensation technique is based on the concept of an inverse process dependency between \(\beta \left( { = \mu C_{OX} {W \mathord{\left/ {\vphantom {W L}} \right. \kern-0pt} L}} \right)\) and the threshold voltage \(V_{TH}\) of the MOS transistor at any process corner. A current reference of 100 nA is implemented in CMOS 0.18 µm technology and studied through simulation. The proposed circuit has a temperature coefficient of 335 ppm/°C in the temperature range of 0–100 °C. It provides a low process variation of ± 2.1% and a lower line sensitivity of 0.093%/V in the supply voltage range of 1.35–3 V. It achieves a better figure of merit of 5.487% compared to the current references reported in the literature.

Keywords

Nano-ampere current reference Temperature compensation Proportional to absolute temperature (PTAT) current generator Process compensation Line sensitivity 

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringNational Institute of TechnologyTiruchirappalliIndia
  2. 2.Open-Silicon Research PVT LimitedBangaloreIndia

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