A 12bit 250MSPS pipeline ADC with 4 Gbps serial output interface
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A 12bit 250MSPS pipeline analog-to-digital converter (ADC) with serial output interface is presented. The pseudo random digital calibration dithered sub-ADC in first stage is used to lower non-ideal errors and improve the dynamic performance in the high speed ADC. An integrated serial output interface is implemented to convert 12bit parallel data into a differential serial data stream. The pipeline ADC was fabricated with CMOS 180 nm 1.8 V 1P5 M process. The active ADC with the serial output interface consumes a power consumption of 395 mW and occupies an area of 8.0 mm2, where the active area of the interface is 0.75 mm2. The measurement results show that the differential non-linearity and integral non-linearity of the proposed ADC are − 0.22/+ 0.16LSB and − 0.4/+ 0.6LSB, respectively. The spurious free dynamic range and signal-to-noise ratio can get 81.17 dB and 69.92 dB with 20 MHz input signal at full sampling speed. The serial output interface provides an eye height greater than 800 mV for data rates of 4 GHz bits per second with a power of 75 mW.
KeywordsPipeline ADC Pseudo random PLL Interface
This work was supported by Natural Science Foundation of China (No. 61704161), Higher Education Important Science Foundation of Anhui Province (No. KJ2017A396) and Guangzhou Industry-Academia-Research Program (No. 201604016122). The authors would like to thank analog group for the technical discussions, layout and test group for their layout and test contributions.
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