A 20 GHz subharmonic injection-locked clock multiplier with mixer-based injection timing control in 65 nm CMOS technology
- 59 Downloads
This paper presents a 20 GHz subharmonic injection-locked clock multiplier (SILCM), which adopts a mixer based self-align injection timing control loop to guarantee the optimal injection point. In addition, to further improve the injection time accuracy and reduce the super, a V/I mismatch cancellation are utilized. Furthermore, a frequency-locked loop with a frequency-lock detection and enable control switch is employed to expand the injection-locked range and save power. Fabricated in a 65 nm CMOS technology, the SILCM can lock from 19.2 GHz to 23.2 GHz. It exhibits − 125.5 dBc/Hz phase noise at 1 MHz offset and consumes 8 mW under 1.2 V power supply. The measured root-mean-square jitter integrating from 0.1 kHz to 100 MHz is 106 fs and the reference spur is − 43 dB.
KeywordsSub-harmonic injection-locked Injection timing control loop Phase noise Mixer Low power
This work is supported by National Science Technology Major Project (No. 2016ZX01012101).
- 1.Zheng, X. Q., et al. (2016). A 5–50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS. In IEEE ESSCIRC Digest of Technical Papers (pp. 305–308), Sept. 2016.Google Scholar
- 4.Ali, T. A., et al. (2011). A 4.6 GHz MDLL with − 46 dBc reference spur and aperture position tuning. In IEEE ISSCC Digest of Technical Papers (pp. 466–468), Feb. 2011.Google Scholar
- 6.Farjad-Rad, R., et al. (2002). A 0.2–2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data-communication chips. In IEEE ISSCC Digest of Technical Papers (pp. 56–57), Feb. 2002.Google Scholar
- 7.Gao, X., et al. (2009). A 2.2 GHz 7.6 mW sub-sampling PLL with − 126 dBc/Hz in-band phase noise and 0.15 ps RMS Jitter in 0.18 μm CMOS. In IEEE ISSCC Digest of Technical Papers (pp. 392–393), Feb. 2009.Google Scholar
- 8.Liang, C. F., & Hsiao, K. J. (2011). An injection-locked ring PLL with self-aligned injection window. In IEEE ISSCC Digest of Technical Papers (pp. 90–92), Feb. 2011.Google Scholar
- 9.Ye, S., et al. (2002). A multiple-crystal interface PLL with VCO realignment to reduce phase noise. IEEE Journal of Solid-State Circuits, 37(x), 1795–1803.Google Scholar
- 11.Elkholy, A., et al. (2015). A 6.75-to-8.25 GHz 2.25 mW 190 fs rms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65 nm CMOS. In IEEE ISSCC Digest of Technical Papers (pp. 22–26), Feb. 2015.Google Scholar
- 13.Ting Le, I., et al. (2013). A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing. In IEEE ISSCC Digest of Technical Papers (pp. 414–415), Feb. 2013.Google Scholar
- 16.Huang, Y.-C. , & Liu, S.-I. (2012). A 2.4 GHz sub-harmonically injection-locked PLL with self-calibrated injection timing. In IEEE ISSCC Digest of Technical Papers (pp. 338–339), Feb. 2012.Google Scholar
- 17.Gao, X., et al. (2010). A 2.2 GHz sub-sampling PLL with 0.16 ps RMS jitter and − 125 dBc/Hz in-band phase noise at 700 μW loop-components power. In IEEE Symposium on VLSI Circuits Digest of Technical Papers (pp. 139–140), June 2010.Google Scholar