A novel low power flip-flop design using footless scheme
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A low power true-single-phase clocking flip-flop (FF) design by using FootLess scheme named FLFF design targeting low VDD and low power operations is proposed. It is adapted from a recently presented FF design and achieves circuit simplification by using hybrid logic style. The optimization measure leads to a new design featuring better both power and speed performances. Based on the simulation results, the proposed design outperforms the conventional transmission gate flip-flop (TGFF) by 84% in energy. An 8-bit Johnson-counter consisting of the proposed FF design is developed and implemented. For the target 250 MHz working frequency, the proposed design achieves over 48.3% power saving with 14.6% area reducing.
KeywordsLow power Complementary pass logic Flip-flop True single-phase clocking
This work was supported by the Ministry of Science and Technology, Taiwan, under Contract No. 106-2221-E-324-022- and No. 107-2221-E-324-017-MY2. The authors also thank the National Chip Implementation Center (CIC), Taiwan for technical support in simulations.
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