Analog Integrated Circuits and Signal Processing

, Volume 98, Issue 2, pp 357–366 | Cite as

A novel 8T SRAM with improved cell density

  • B. Naresh Kumar ReddyEmail author
  • Ch. Ramalingaswamy
  • R. Nagulapalli
  • Dharavath Ramesh


Low voltage and high-density SRAM memory creates new challenges such as stability and sense margin. Conventional decoupled 8T SRAM cell has improved read stability but small sense margin and high leakage power which makes it unsuitable for small supply and high density memories. Proposed decoupled 8T SRAM cell improves sense margin during reading by reducing data leakage current of neighboring SRAM cells which are OFF and write stability by using negative bit line scheme. It is evident from the simulation results that proposed 8T SRAM minimizes leakage current by 49.2% when compared to conventional 8T SRAM cell. It gives stable read for 20.2 K cells per bitline at 0.8 V at room temperature but conventional 8T SRAM can give successful read for 5.83 K cells.


Memory Stability SRAM cell Sense margin Leakage power 


  1. 1.
    Seevinck, E., List, F. J., & Lohstroh, J. (1987). Static-noise margin analysis of MOS SRAM cells. IEEE Journal of Solid-State Circuits, 22(5), 748–754.CrossRefGoogle Scholar
  2. 2.
    Bhavnagarwala, A. J., Tang, X., & Meindl, J. D. (2001). The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE Journal of Solid-State Circuits, 36(4), 658–665.CrossRefGoogle Scholar
  3. 3.
    Guo, Z., Carlson, A., Pang, L. T., Duong, K., Liu, T.-J. K., & Nikolic, B. (2008). Large-scale read/write margin measurement in 45 nm CMOS SRAM arrays. In IEEE symposium on VLSI circuits (pp. 42–43).Google Scholar
  4. 4.
    Zhu, H., & Kursun, V. (2014). A comprehensive comparison of data stability enhancement techniques with novel nanoscale SRAM cells under parameter fluctuations. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(5), 1473–1484.CrossRefGoogle Scholar
  5. 5.
    Chang, L. (2008). An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches. IEEE Journal of Solid-State Circuits, 43(4), 956–963.CrossRefGoogle Scholar
  6. 6.
    Kim, T. H., Liu, J., Keane, J., & Kim, C. H. (2007). A high-density sub threshold SRAM with data-independent bit line leakage and virtual ground replica scheme. In IEEE solid-state circuits conference, ISSCC.Google Scholar
  7. 7.
    Calhoun, B. H., & Chandrakasan, A. (2007). A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation. IEEE Journal of Solid-State Circuits, 42(3), 680–688.CrossRefGoogle Scholar
  8. 8.
    Kim, T., et al. (2009). A voltage scalable 0.26 V, 64 kb 8T SRAM with \(V_{min}\) lowering techniques and deep sleep mode. IEEE Journal of Solid State Circuits, 44(6), 1785–1795.CrossRefGoogle Scholar
  9. 9.
    Li, I., Wang, B., & Kim, T. T. (2012). A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bit lines and fast local write-back for cell stability improvement. In Proceedings of the European solid-state device research conference (ESSDERC) (pp. 201–204).Google Scholar
  10. 10.
    Wang, B., Nguyen, T. Q., Do, A. T., Zhou, J., Je, M., & Kim, T. T. (2012). A 0.2 V 16 Kb 9T SRAM with bit line leakage equalization and CAM-assisted write performance boosting for improving energy efficiency. IEEE Asian solid state circuits conference (A-SSCC) (pp. 73–76).Google Scholar
  11. 11.
    Chang, I., Kim, J., Park, S., & Roy, K. (2008). A 32 b 10T sub threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS. In IEEE international solid-state circuits conference digest of technical papers.Google Scholar
  12. 12.
    Kim, T. T., & Ba, N. L. (2013). A low voltage 8-T SRAM with PVT-tracking bit line sensing margin enhancement for high operating temperature. In IEEE Asian solid state circuits conference (A-SSCC) (pp. 233–236).Google Scholar
  13. 13.
    Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oda, Y., Usui, K., Kawamura, T., Tsuboi, N., Iwasaki, T., Hashimoto, K., Makino, H., & Shinohara, H. (2008). A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. In IEEE symposium on VLSI circuits (pp. 212–213).Google Scholar
  14. 14.
    Fujimura, Y., Hirabayashi, O., Sasaki, T., Suzuki, A., Kawasumi, A., Takeyama, Y., Kushida, K., Fukano, G., Katayama, A., Niki, Y., & Yabe, T. (2010). A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149 \(um^2\) cell in 32 nm high-k metal-gate CMOS. In IEEE international on solid-state circuits conference digest of technical papers (ISSCC) (pp. 348–349).Google Scholar
  15. 15.
    Shibata, N., Kiya, H., Kurita, S., Okamoto, H., Tanno, M., & Douseki, T. (2006). A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment—sure write operation by using step-down negatively overdriven bitline scheme. EEE Journal of Solid-State Circuits, 41(3), 728–742.CrossRefGoogle Scholar
  16. 16.
    Mukhopadhyay, S., Rao, R., Kim, J.-J., & Chuang, C.-T. (2011). SRAM write-ability improvement with transient negative bit-line voltage. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(1), 24–32.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electronics and Computer EngineeringK.L.UniversityGunturIndia
  2. 2.Department of Computer Science EngineeringMahindra Ecole Centrale College of EngineeringHyderabadIndia
  3. 3.Department of Electronics and CommunicationOxford Brookes University, Wheatley CampusWheatleyUK
  4. 4.Department of Computer Science EngineeringIndian Institute of Technology (ISM), DhanbadDhanbadIndia

Personalised recommendations