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Analog Integrated Circuits and Signal Processing

, Volume 98, Issue 1, pp 169–179 | Cite as

Resource minimization and power reduction of ESPFFIR filter using unified adder/subtractor

  • R. Solomon RoachEmail author
  • N. Nirmal Singh
  • T. S. Arun Samuel
Article
  • 17 Downloads

Abstract

Digital filters are the important processing elements in most of the digital signal processing system designs, ranging from medical signal processing to wireless communication. Low power and area efficient Finite Impulse Response filter is designed with the aid of parallel processing which increases the throughput. Symmetric property reduces the multipliers into half in Even Symmetric Parallel Fast Finite Impulse Response (ESPFFIR) filters. The adder and the subtractor present in the pre/post-processing blocks increase in accordance with the block size L of ESPFFIR filter which in turn increases the numbers of unified operators. The canonical signed digit representation of the coefficient in the design Multiple Constant Multiplications (MCM) based multipliers has the advantages of utilizing unified operators in sub-filter block of ESPFFIR. To reduce the power consumption and resource utilization of the ESPFFIR filter, the unified operator used in the pre/post processing and MCM blocks are replaced by unified adder subtractor (UAS). The UAS utilizes fewer resources for simultaneous calculation of sum and difference of two operands with less area and low power consumption. This paper shows the design of 16-bit Square Root (SQRT) UAS CSLA adder using UAS logical element to reduce the area utilization, power consumption and delay. Then the Heuristic of cumulative benefit (Hcub) based MCM multiplier is designed using UAS. The existing SQRT BEC CSLA adder and subtractor with same input present in the pre/post processing block of the ESPFFIR filters are replaced by a single SQRT UAS CSLA in suitable places. The Hcub MCM used in the sub-filter blocks of the ESPFFIR are replaced using SQRT UAS CSLA based MCM multiplier. The SQRT UAS CSLA consumes 78% less area, 29.51% less power and 24% less delay when compared to the BEC CSLA 2 (one BEC based CSLA Adder plus one BEC based CSLA Subtractor). Finally, the SQRT UAS CSLA adder and Hcub based UAS MCM multipliers are used to design the filter, the overall area and power consumption of UAS based ESPFFIR is reduced compared with the existing BEC based ESPFFIR filter. Cadence RC tool is used for analysis.

Keywords

Unified adder/subtractor (UAS) Binary to excess-1 converter (BEC) Even Symmetric Parallel Fast Finite Impulse Response (ESPFFIR) Carry select adder (CSLA) 

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringCape Institute of TechnologyLevinjipuram, TirunelveliIndia
  2. 2.Department of Electronics and Communication EngineeringVV College of EngineeringTirunelveliIndia
  3. 3.Department of Electronics and Communication EngineeringNational Engineering CollegeKovilpattiIndia

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