Analog Integrated Circuits and Signal Processing

, Volume 98, Issue 1, pp 169–179 | Cite as

Resource minimization and power reduction of ESPFFIR filter using unified adder/subtractor

  • R. Solomon RoachEmail author
  • N. Nirmal Singh
  • T. S. Arun Samuel


Digital filters are the important processing elements in most of the digital signal processing system designs, ranging from medical signal processing to wireless communication. Low power and area efficient Finite Impulse Response filter is designed with the aid of parallel processing which increases the throughput. Symmetric property reduces the multipliers into half in Even Symmetric Parallel Fast Finite Impulse Response (ESPFFIR) filters. The adder and the subtractor present in the pre/post-processing blocks increase in accordance with the block size L of ESPFFIR filter which in turn increases the numbers of unified operators. The canonical signed digit representation of the coefficient in the design Multiple Constant Multiplications (MCM) based multipliers has the advantages of utilizing unified operators in sub-filter block of ESPFFIR. To reduce the power consumption and resource utilization of the ESPFFIR filter, the unified operator used in the pre/post processing and MCM blocks are replaced by unified adder subtractor (UAS). The UAS utilizes fewer resources for simultaneous calculation of sum and difference of two operands with less area and low power consumption. This paper shows the design of 16-bit Square Root (SQRT) UAS CSLA adder using UAS logical element to reduce the area utilization, power consumption and delay. Then the Heuristic of cumulative benefit (Hcub) based MCM multiplier is designed using UAS. The existing SQRT BEC CSLA adder and subtractor with same input present in the pre/post processing block of the ESPFFIR filters are replaced by a single SQRT UAS CSLA in suitable places. The Hcub MCM used in the sub-filter blocks of the ESPFFIR are replaced using SQRT UAS CSLA based MCM multiplier. The SQRT UAS CSLA consumes 78% less area, 29.51% less power and 24% less delay when compared to the BEC CSLA 2 (one BEC based CSLA Adder plus one BEC based CSLA Subtractor). Finally, the SQRT UAS CSLA adder and Hcub based UAS MCM multipliers are used to design the filter, the overall area and power consumption of UAS based ESPFFIR is reduced compared with the existing BEC based ESPFFIR filter. Cadence RC tool is used for analysis.


Unified adder/subtractor (UAS) Binary to excess-1 converter (BEC) Even Symmetric Parallel Fast Finite Impulse Response (ESPFFIR) Carry select adder (CSLA) 


  1. 1.
    Gately, M. B., Yeary, M. B & Tang, C. Y. (2012). Multiple real-constant multiplication with improved cost model and greedy and optimal searches. In Proceedings of IEEE international symposium on circuits and systems, Seoul, Korea (pp. 588–591).Google Scholar
  2. 2.
    Hartley, R. I. (1996). Sub expression sharing in filters using canonic signed digit multipliers. IEEE Transactions on Circuits and Systems II, 43(10), 677–688.CrossRefGoogle Scholar
  3. 3.
    Kumm, M., Zipf, P., Faust, M., & Chang, C. H. (2012). Pipelined adder graph optimization for high speed multiple constant multiplication. In Proceedings of IEEE international symposium on circuits and systems, Seoul, Korea (pp. 49–52).Google Scholar
  4. 4.
    Voronenko, Y., & PuSchel, M. (2007). Multiplierless multiple constant multiplication. ACM Transactions on Algorithms, 3(2), 2007.MathSciNetCrossRefzbMATHGoogle Scholar
  5. 5.
    Cheng, C., & Parhi, K. K. (2004). Hardware efficient fast parallel FIR filter structures based on iterated short convolution. IEEE Transactions on Circuits and Systems I., 51(8), 1492–1500.MathSciNetCrossRefzbMATHGoogle Scholar
  6. 6.
    Chung, J. G., & Parhi, K. K. (2002). Frequency-spectrum-based low-area low-power parallel FIR filter design. EURASIP Journal on Advances in Signal Processing, 2002(9), 444–453.CrossRefzbMATHGoogle Scholar
  7. 7.
    Parker, D. A., & Parhi, K. K. (1997). Low-area/power parallel FIR digital filter implementations. Journal of VLSI Signal Processing Systems, 17(1), 75–92.CrossRefGoogle Scholar
  8. 8.
    Tsao, Y.-C., & Choi, K. (2012). Area-efficient parallel FIR digital filter structures for symmetric convolutions based on fast FIR algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(2), 366–371.CrossRefGoogle Scholar
  9. 9.
    Tsao, Y.-C., & Choi, K. (2012). Area-efficient VLSI implementation for parallel linear-phase FIR digital filters of odd length based on fast FIR algorithm. IEEE Transactions on Circuits and Systems-II: Express Briefs, 59(6), 371–375.CrossRefGoogle Scholar
  10. 10.
    Solomon Roach, R., & Nirmal Singh, N. (2016). Design of low power and area efficient ESPFFIR filter using multiple constant multiplier. Revista Tecnica de la Facultad de Ingenieria Universidad del Zulia., 39(6), 214–225.Google Scholar
  11. 11.
    Ramkumar, B., & Kittur, H. M. (2012). Low-power and area-efficient carry select adder. IEEE Transactions on Very Large Scale Integeration Systems, 20(2), 371–375.CrossRefGoogle Scholar
  12. 12.
    Peiro, M. M., Boemo, E. I., & Wanhammar, L. (2002). Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm. IEEE Transactions on Circuits and Systems II, 49(3), 196–203.CrossRefGoogle Scholar
  13. 13.
    Xu, F., Chang, C. H., & Jong, C. C. (2005). Modified reduced adder graph algorithm for multiplierless FIR filters. Electronics Letters, 41(6), 302–303.CrossRefGoogle Scholar
  14. 14.
    Xu, F., Chang, C. H., & Jong, C. C. (2005). Contention resolution algorithms for common subexpression elimination in digital filter design. IEEE Transactions on Circuits and Systems II, 52(10), 695–700.CrossRefGoogle Scholar
  15. 15.
    Xu, F., Chang, C. H., & Jong, C. C. (2008). Contention resolution: A new approach to versatile subexpressions sharing in multiple constant multiplications. IEEE Transactions on Circuits and Systems I, 55(2), 559–571.MathSciNetCrossRefGoogle Scholar
  16. 16.
    Hormigo, J., Villalba, J., & Zapata, E. L. (2013). Multioperand redundant adders on FPGAs. IEEE Transactions on Computers, 62(10), 2013–2025.MathSciNetCrossRefzbMATHGoogle Scholar
  17. 17.
    Han, L., Zhang, H., & Ko, S.-B. (2015). Area and power efficient decimal carry-free adder. IET Journals and Magazines, Electronics Letters, 51(23), 1852–1854.CrossRefGoogle Scholar
  18. 18.
    Ding, J., Chen, J., & Chang, C.-H. (2016). A new paradigm of common sub expression elimination by unification of addition and subtraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(10), 1605–1617.CrossRefGoogle Scholar

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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringCape Institute of TechnologyLevinjipuram, TirunelveliIndia
  2. 2.Department of Electronics and Communication EngineeringVV College of EngineeringTirunelveliIndia
  3. 3.Department of Electronics and Communication EngineeringNational Engineering CollegeKovilpattiIndia

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