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Analog Integrated Circuits and Signal Processing

, Volume 98, Issue 1, pp 155–167 | Cite as

A 0.9 V 3rd-order single-opamp analog filter in 28 nm bulk-CMOS

  • Stefano D’AmicoEmail author
  • Marcello De Matteis
  • Andrea Donno
  • Andrea Baschirotto
Article
  • 70 Downloads

Abstract

This paper presents a 28 nm-bulk-CMOS 3rd-order 132 MHz low-pass filter based on an improved Active-gm-RC stage. Challenges related to the design of analog circuits in 28 nm-bulk-CMOS process node are faced, mitigated and exploited by operating at both architecture and circuit design levels. The filter uses a single-opamp two-stage topology where both poles are used for synthesizing a 3rd-order low-pass transfer function. The proposed filter operates from a single 0.9 V supply voltage, consumes 340 µW and performs high linearity (IIP3 = 11.5 dBm at 21 and 22 MHz input tones) and large Signal-to-Noise ratio (58 dB). This enables one of the higher Figure-of-Merit (163.2 dB) with respect to the state-of-the-art.

Keywords

Analog filter Continuous time Low-voltage circuits CMOS 28 nm Low-power circuits 

Notes

Acknowledgements

This activity is within the ScalTech28 project funded by INFN (Italian National Institute for Nuclear Physics).

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Innovation EngineeringUniversity of SalentoLecceItaly
  2. 2.Department of PhysicsUniversity of Milan-BicoccaMilanItaly
  3. 3.Istituto Italiano di Fisica NucleareMilanItaly
  4. 4.Thetis Microelectronics srlsLecceItaly

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