Experimental implementation of a 14 bit 80 kSPS non-binary cyclic ADC
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This paper presents a prototype of 14 bit 80 kSPS non-binary cyclic ADC without high accuracy analog components and complicated digital calibration. Since the redundancy of non-binary ADC tolerates the non-idealities of analog components such as capacitor mismatch and finite amplifier DC gain, the design consideration of this high accuracy ADC can be only focused on the capacitance of sampling capacitor to satisfy the overall kT/C noise target, the drivability and linearity of amplifier without any high accuracy analog components. The proposed proof-of-concept cyclic ADC has been designed and fabricated in TSMC 90 nm CMOS technology. Measured SNDR = 81.9 dB is achieved at Fs = 80 kSPS with a simple radix-value estimation technique. No other complicated digital calibration is used to compensate the non-linearity of ADC caused by MOM capacitors and a poor gain of the amplifier as low as 66 dB. Measured DNL is − 0.6/+ 0.67 LSB and INL is − 1.2/+ 1.6 LSB. Prototype ADC dissipates 8mW at supply voltage is 3.3 V in analog circuits.
KeywordsNon-binary ADC Cyclic ADC Radix estimation
The authors would like to thank STARC for supporting this research.
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