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Analog Integrated Circuits and Signal Processing

, Volume 96, Issue 3, pp 495–507 | Cite as

Analysis of switched-capacitor circuits using driving-point signal-flow graphs

  • Hanspeter Schmid
  • Alex Huber
Open Access
Article
  • 429 Downloads

Abstract

This paper extends the driving-point signal-flow graphs to switched-capacitor (SC) circuits by introducing a new theoretical element: an auxiliary voltage source that transfers no charge. In contrast to existing SFG methods, our method has no restrictions as to what types of SC circuits can be analysed, it requires no equivalent circuits or tables, and it works with two-phase as well as multi-phase SC circuits of any complexity. Compared to charge-equation matrix methods, it requires more effort, but is better suited for hand analysis because it makes causal relationships visible. Three illustrative examples are given to show the efficiency of the method and present a few application hints: a voltage doubler, the standard SC integrator, and a four-phase circuit simulating an inductor.

Keywords

Switched-capacitor circuits Signal-flow graph Driving-point impedance Multi-phase SC networks Circuit analysis 

1 Introduction

Switched-capacitor (SC) circuits are analog discrete-time circuits that consist of switches, capacitors, and amplifiers. They are as diverse and powerful as they are hard to analyse. This is mainly so because SC circuits reconfigure between phases, so they will not have the same topology, nor even the same number of nodes, in the different phases.

Signal-flow graphs (SFGs) are often used for hand analysis of circuits (and for teaching), because they make causal relationships visible and provide insight into a circuit even before transfer functions are calculated [1, 2, 3, 4]. While the SFG analysis of arbitrary continuous-time circuits is solved, there is no SFG method yet that can be applied to all SC circuits without restrictions on their structure or number of phases. In this paper we propose such an SFG method, compare it to previous SFG method to highlight the improvement, and compare it to the established charge-equation method to show that it describes the same equation systems in a different way.

The DPSFG was introduced in 1998 [5] when Ochoa combined driving-point impedance techniques with Mason signal-flow graphs (SFGs) [6, 7]. Ochoa used auxiliary voltage generators (which we call auxiliary voltage sources or aux sources) and explained the SFG derivation by first splitting schematics into sub-circuits and then coupling the sub-circuits with voltage-controlled current sources.

We cast Ochoa’s method into a different cognitive framework in [8], making it unnecessary to resort to intermediate circuit representations and simplifying the application of the method to the point where no written material or tables at all are required to use it. This way of explaining the method followed closely Mason’s original idea to use SFGs because they “offer a visual structure, a universal graph language, a common ground upon which causal relationships among a number of variables may be laid out and compared [7]”. The one-to-one correspondence between circuit and graph also made it straightforward to derive transposed circuits, as shown in [8].

Concerning SC networks, two groups devised and published general analysis methods in parallel. The first publication used the concepts of nodal analysis on SC circuits and also extended classical two-port theory to SC circuits [9]. In the second publication, the derivation of the matrices is simpler, because it uses a switch matrix that is straightforward to derive, but since the author does not use the z transform, but only discrete-time equations with time indices, the derivations do not result in z transfer functions [10].

The nodal analysis was then further simplified by using the indefinite admittance matrix (IAM) in [11] and was extended to the analysis of multiphase SC networks [12]. Since there is a very close correspondence between signal-flow graphs and IAMs, SFGs started to be used at that point in time because, by making causal relationships and signal flow visible, authors gained more insight into the circuits.

The first comprehensive paper about SFG analysis of SC circuits was published in 1984 [13], it bases on the theory introduced in [11] and makes it possible to easily assemble signal-flow graphs of SC filters by first tabulating basic building blocks and the corresponding graph parts. This method was extended to multiphase SC networks [14].

Both [13] and [14] succeed in making the signal flow visible, but the graphs are not one-to-one maps of the circuits. Furthermore, the methods only work for source-sink-node (SSN) networks [14], which means that all nodes are either at a voltage source or at an amplifier input. Many circuits, e.g., those doing correlated double sampling and voltage multiplication, are therefore not covered.

These methods assume from the start that there are no parasitic capacitors and that the gain of the op-amps used in the SC circuits is infinite. They cannot possibly analyse the effect of finite opamp gain on the transfer functions, which is quite important, as was, e.g., discussed in [15] for SC integrators.

This was remedied in Chichocki et al. [16] who made it possible to analyse any SC circuit, with non-ideal op-amps and also parasitic capacitors. They used a small number of equivalent z-domain circuits and the Coates flow-graph technique. In their own words, they “require a smaller number of elements than the equivalent circuits previously proposed”. But they still require equivalent circuits containing some additional elements.

In a previous paper we applied DPSFGs to the noise analysis in SC circuits, [17]. In this paper, we introduce a DPSFG analysis method for SC circuits that requires no equivalent circuits whatsoever and imposes no restrictions on amplifier gains, parasitic capacitors, or the number of clock phases. What results is a general method for visual-based (i.e., intuitive) analysis of switched-capacitor networks of any complexity, with any number of phases.

As in all cited papers, the theory is simple (here it is the introduction of a new type of auxiliary voltage source). We want to show that this one intuitive understanding—the understanding of that new aux source—makes it possible to analyse continuous-time and switched-capacitor circuits with the same SFG technique. The purpose of this paper is to extend and unify SFG analysis and enable SFG users to tackle all SC circuits as easily as they can treat continuous-time circuits.

Therefore, we proceed as follow: In Sect. 2, we give a short introduction to SFGs and DPSFGs of continuous-time circuits. Our explanation complements [4, 5, 8]; it is structured such that the introduction of the new theoretical element is as simple as possible in Sect. 3, where we also give a minimal example. Section 4 contains the main example in which we show how to efficiently apply our method. Section 5 extends this to multi-phase networks and shows how to calculate a discrete-time input impedance. Finally, in Sect. 6 we show what to do when graphical evaluation becomes too complicated.

2 Driving-point signal-flow graphs (DPSFG) of continuous-time circuits

This section presents the DPSFG method introduced in [5], brought to its present form in [8], and provided as a sequence of video tutorials in [4].

2.1 Signal-flow graphs and Mason’s gain rule

Mason graphs are just graphical representations of linear equation systems. The so-called branches are multipliers, and the so-called nodes are variables. All branches going into a node are added. Therefore, each node that has branches going into it describes a linear equation, and the example shown in Fig. 1 represents the following linear equation system:
$$\begin{aligned} v & = au+fw+gx,\nonumber \\ w & = bv, \nonumber \\ x & = cw, \nonumber \\ y & = ku+dx+hz,\nonumber \\ z & = ey. \end{aligned}$$
(1)
This can also be expressed in matrix notation:
$$\begin{aligned} \begin{pmatrix} v\\ w\\ x\\ y\\ z \end{pmatrix} & = \begin{pmatrix} \cdot &f&g&\cdot &\cdot \\ b&\cdot &\cdot &\cdot &\cdot \\ \cdot &c&\cdot &\cdot &\cdot \\ \cdot &\cdot &d&\cdot &h\\ \cdot &\cdot &\cdot &e&\cdot \end{pmatrix} \begin{pmatrix} v\\ w\\ x\\ y\\ z \end{pmatrix} + \begin{pmatrix} a\\ \cdot \\ \cdot \\ k\\ \cdot \end{pmatrix} \,u, \end{aligned}$$
(2)
where we have simply replaced all numbers 0 by \(\cdot\) such that it becomes immediately apparent that this graph corresponds to a sparse-matrix equation system.
Fig. 1

Example of a signal-flow graph (SFG) with nodes uvwxyz and path weights abcdefghk. This graph represents a linear equation system with five dependent variables, vwxyz, five equations, and one independent variable u

It would be equally simple to take any matrix equation, e.g., an IAM representation of a circuit, and draw it as a Mason graph, but that would not necessarily be helpful as it would then not show the causal relationships.

Equation (2) could now be solved by matrix manipulations, but Mason showed a better way in [7]: A transfer function from a node u to a node z can be calculated as
$$\begin{aligned} T & = \frac{z}{u} = \frac{\sum _i P_i\,\Delta _i}{\Delta }. \end{aligned}$$
(3)
The graph determinant \(\Delta\) can be calculated as
$$\begin{aligned} \Delta & = 1 - \sigma _1 + \sigma _2 - \sigma _3 + \cdots = 1-\sum _1^{\infty } (-1)^i \sigma _i , \end{aligned}$$
(4)
where \(\sigma _1\) is the sum of all loops, \(\sigma _2\) is the sum of products of 2 loops that do not have nodes in common, and \(\sigma _3\) is the sum of products of 3 loops neither of which have nodes in common, and so on. The sum (4) can, in principle, go to \(\sigma _N\) in a system with N loops, but most feedback systems derive their special properties from interacting loops, so the sum often ends soon in practice. In more technical terms, whenever a matrix representation of the equation system would be sparse, then Mason’s formula is efficient.
In Fig. 1, we have three loops:
$$\begin{aligned} L_1&= bf,\quad L_2=bcg,\quad L_3=eh. \end{aligned}$$
(5)
\(L_1\) and \(L_2\) have nodes in common, but \(L_3\) touches neither of the other loops, so (4) becomes
$$\begin{aligned} \Delta & = 1-L_1-L_2-L_3+L_1L_3+L_2L_3. \end{aligned}$$
(6)
The \(P_i\) in the numerator of (3) are the forward paths, the possible ways to get from u to z. The \(\Delta _i\) are their respective sub-determinants, which are calculated just like \(\Delta\), but only using loops that have no nodes in common with the forward path in question.
In Fig. 1, we have two forward paths:
$$\begin{aligned} P_1&= abcde,\quad P_2=ke. \end{aligned}$$
(7)
Path \(P_1\) touches all loops, so when calculating the sub-determinant, all terms containing loops in (6) disappear and \(\Delta _1=1\). Path \(P_2\) only touches loop \(L_3\), so all terms containing \(L_3\) in (6) have to be omitted to calculate \(\Delta _2=1-L_1-L_2\).
Inserting everything into (3) results in
$$\begin{aligned} T&= \frac{abcde + ke\left( 1-bf-bcg\right) }{1-bf-bcg-eh+befh+bcegh}. \end{aligned}$$
(8)
Note that if a different transfer function has to be calculated (e.g., \(T_y=y/u\)), then only the numerator can change, because \(\Delta\) does not depend on the forward paths.

Mathematically, an SFG is just a graphical representation of an equation system, which can even be manipulated and simplified graphically [6]. But as Mason stated there, it can also be used to visualise causal relationships—if it is drawn in the right way.

2.2 The driving-point signal-flow graph (DPSFG)

The most important aspect of a signal-flow graph that is to be used for hand analysis is that it maintains and represents causal relationships. The common tool used in literature is source superposition, as it is also done when circuit equations are derived from circuits.

Source superposition will give individual contributions from all sources to all circuit nodes for the condition that all other sources are set to zero. So unless there is a voltage source in every node of a circuit, it is necessary to tabulate all possible networks that could reasonably appear between sources and sinks, which invariably means restricting methods to certain classes of circuits, or to use another analysis method to derive the individual contributions.

As explained in [8], the DPSFG method solves this problem by making sure there is a voltage source at every circuit node. In order to achieve this, the first step in circuit analysis is to introduce an auxiliary source (aux source) at every node that does not yet have a voltage source. This aux source is defined as follows: It produces the voltage that is already present at a node, and therefore conducts no current.

To give an example, Fig. 2(a) shows the standard continuous-time integrator with a resistor having conductance G and a capacitor having capacitance C, and an opamp having gain A. Node 1 is connected to the input source, node 3 to the opamp output, which is also a voltage source, but there is no voltage source on node 2. Therefore an aux source is connected to node 2, resulting in Fig. 2(b).
Fig. 2

Continuous-time integrator without and with aux source

To draw the DPSFG, we can first draw all nodes. Observe that we also draw the current flowing into the aux source, \(I_2\), in Fig. 3(a).
Fig. 3

The step-wise development of the DPSFG for the circuit in Fig. 2(b)

Then we simply do source superposition, voltage by voltage. \(V_{\mathrm {in}}\) controls \(V_1\), and we have Fig. 3(b). \(V_1\) lets a current \(I_2=G\,V_1\) flow, which gives Fig. 3(c). \(V_2\) controls the opamp output as \(V_3=-A\,V_2\), giving Fig. 3(d). \(V_3\) lets a current \(I_2=sC\,V_3\) flow, and it also is the same as \(V_{\mathrm {out}}\), and we have Fig. 3(e).

This is almost all, but now we have a problem: \(I_2\) is not zero! The aux source was defined to conduct no current. However, \(I_2\) is not the true current into the source, but the current flowing into the aux source for \(V_2=0\): the short-circuit current of the aux source. So one part of the source superposition is missing. In order to have zero current under superposition, we now need to calculate the necessary voltage \(V_2=Z_2\,I_2\) to have \(I_2\) flow out of the aux source when all other sources are set to zero. This is Fig. 3(f).

This \(Z_2\) is the driving-point impedance (DPI) which gives the DPSFG part of its name. Since we have made sure that every node now has a voltage source attached, all of which are set to zero during superposition, this DPI is always the inverse of the sum of all conductances connected to the node. Here,
$$\begin{aligned} Z_2&= \frac{1}{G+sC}. \end{aligned}$$
(9)
This is all, and it becomes apparent that the result is an SFG that shows the causality as well as describing the equation system of the circuit. There is only one loop, and only one path, which even touches the loop. Therefore:
$$\begin{aligned} L_1&= -A\,Z_2\,sC, \end{aligned}$$
(10)
$$\begin{aligned} \Delta&= 1-L_1 = 1+A\,Z_2\,sC,\end{aligned}$$
(11)
$$\begin{aligned} P_1 & = -G\,Z_2\,A,\end{aligned}$$
(12)
$$\begin{aligned} \Delta _1 & = 1,\end{aligned}$$
(13)
$$\begin{aligned} T & = \frac{V_{\mathrm {out}}}{V_{\mathrm {in}}} = \frac{P_1\,\Delta _1}{\Delta } = -\frac{G\,Z_2\,A}{1+A\,Z_2\,sC} \approx -\frac{G}{sC}, \end{aligned}$$
(14)
where the last approximation is for \(A\rightarrow \infty\).
Additional things can now be calculated with comparatively small effort. For example, what happens if a parasitic capacitance \(C_p\) is connected to node 2? Then only \(Z_2\) changes to
$$\begin{aligned} Z_2&= \frac{1}{G+s(C+C_p)}. \end{aligned}$$
(15)
What if we need to know the input admittance? The input current is \(I_{\mathrm {in}}=(V_1-V_2)\,G\). Drawn as SFG branches, this gives Fig. 3(g). The only thing that changes are the forward paths, and we get:
$$\begin{aligned} P_1&= G, \end{aligned}$$
(16)
$$\begin{aligned} \Delta _1&= \Delta ,\end{aligned}$$
(17)
$$\begin{aligned} P_2&= -G^2\,Z_2,\end{aligned}$$
(18)
$$\begin{aligned} \Delta _2&= 1,\end{aligned}$$
(19)
$$\begin{aligned} Y_{\mathrm {in}}&= \frac{I_{\mathrm {in}}}{V_{\mathrm {in}}} = \frac{P_1\,\Delta _1+P_2\,\Delta _2}{\Delta } = G - \frac{G^2\,Z_2}{1+A\,Z_2\,sC}. \end{aligned}$$
(20)
For \(A\rightarrow \infty\), this gives \(Y_{\mathrm {in}}=G\), as expected, because then node 2 is virtual ground.

And this method always works, for every linear circuit. The only thing that happens for larger circuits is that there are more aux sources, and of course Mason’s rule becomes more tedious to evaluate, but the derivation of the branches is never different from, or more difficult than, what we just showed. Note, however, that from a didactic point of view, it can be better to fill in the DPSFG in a different order (c.f. [4, Chap. 7]).

This method works because the aux sources make Kirchhoff current-law (KCL) equations appear in the SFG. We illustrate this by looking at the equations for the aux-source-related nodes \(I_2\) and \(V_2\):
$$\begin{aligned} I_2&= V_1\,G + V_3\,sC, \end{aligned}$$
(21)
$$\begin{aligned} V_2&= Z_2\,I_2. \end{aligned}$$
(22)
We insert (22) into (21), take all sum terms to the same side, and collect expressions with G and sC:
$$\begin{aligned} \left( V_1-V_2\right) \,G + \left( V_3-V_2\right) \,sC&= 0. \end{aligned}$$
(23)
And we see that this is the KCL for node 2.

In summary, the connection of an aux source causes the KCL equation for that node to appear in the graph. This is basically why the DPSFG method must work for any linear circuit.

3 The charge-mode auxiliary source

At this point we are ready to extend the method to SC circuits. After the lengthy introduction it is clear that (a) SC circuits reconfigure when the phases change, and (b) if the proper auxiliary source is chosen, then source superposition becomes simple and drawing an SFG becomes straightforward.

Theorem 1

The DPSFG method as introduced in [5], and as presented without the need to split a circuit into sub-circuits in Sect. 2, works for all SC circuits with an arbitrary number of phases if (a) one circuit diagram per phase is drawn, with switches shorted or opened, and (b) in each of those circuit diagrams, auxiliary sources are attached to all nodes that are not connected to a voltage source. Such an aux source is defined as follows: It produces the voltage that is already present at a node, and therefore conducts no charge.

The validity of this theorem will now be demonstrated by giving examples. Figure 4 shows an SC voltage doubler, a simple SC circuit, which nevertheless is not a source-sink network. The figure shows the circuit with the switches, and the two circuit configurations in the odd phase (phase 1) and the even phase (phase 2). We have given all nodes individual numbers.
Fig. 4

Inverting capacitive voltage doubler. Top: circuit with all switches. Centre: phase 1 (odd). Bottom: phase 2 (even), with aux sources. (Note: Normally non-inverting doublers are used, but the inverting-doubler schematic is easier to read and thus better suited to discuss an analysis method.)

Node 1 in the odd phase is at a voltage source terminal, but nodes 2 and 3 in the even phase are not, so there we attach aux sources. This time the sources have a voltage \(V_{2,3}^{\mathrm {e}}\) and a charge \(Q_{2,3}^{\mathrm {e}}\) that is the charge flowing into the source while the even-phase circuit settles to its final state.

Now we can construct the DPSFG just as in Sect. 2.2 but by using charges and voltages instead of currents and voltages. First we write down all nodes of the SFG, in two rows for the two phases, giving Fig. 5(a). Now source by source: \(V_{\mathrm {in}}^{\mathrm {o}}\) is \(V_1^{\mathrm {o}}\): Fig. 5(b). If all sources other than \(V_1^{\mathrm {o}}\) are set to zero, then \(C_1\) and \(C_2\) are discharged into the aux sources \(V_{2}^{\mathrm {e}}\) and \(V_{3}^{\mathrm {e}}\).

Observing the respective plates of the capacitors discharged into the nodes, and since this is another phase, \(Q_{2}^{\mathrm {e}}=\left( C_2\,z^{-1}-C_1\,z^{-1}\right) \,V_{1}^{\mathrm {o}}\) and \(Q_{3}^{\mathrm {e}}=-C_2\,z^{-1}\): Fig. 5(c). If \(V_{2}^{\mathrm {e}}\) is switched on and all others are zero, a charge \(Q_{3}^{\mathrm {e}}=C_2\,V_{2}^{\mathrm {e}}\) flows: Fig. 5(d). Similarly, if \(V_{3}^{\mathrm {e}}\) is switched on and all others are zero, a charge \(Q_{2}^{\mathrm {e}}=C_2\,V_{3}^{\mathrm {e}}\) flows, and this also is \(V_{\mathrm {out}}^{\mathrm {e}}\): Fig. 5(e).
Fig. 5

The step-wise development of the DPSFG for the circuit in Fig. 4(b)

As in Sect. 2.2, we now have calculated the short-circuit charges of the aux sources and need a last step answering the question: what should the voltage of the aux sources be such that, under superposition, the aux source conducts no charge? This gives Fig. 5(f). Before, we got driving-point impedances in this step, and now we get \(S_{2,3}^{\mathrm {e}}\), which are two driving-point elastances, an elastance being an inverse capacitance (\(\hbox {unit F}^{-1}\)), and obviously
$$\begin{aligned} S_{2}^{\mathrm {e}}&= \frac{1}{C_1+C_2},\quad S_{3}^{\mathrm {e}} = \frac{1}{C_2}, \end{aligned}$$
(24)
for the exact same reason why driving-point impedances have this structure.
Mason’s rule is simple since there is only one loop and two forward paths that touch the loop:
$$\begin{aligned} L_1&= S_{2}^{\mathrm {e}} C_2 S_{3}^{\mathrm {e}} \, C_2, \end{aligned}$$
(25)
$$\begin{aligned} \Delta &= 1-L_1,\end{aligned}$$
(26)
$$\begin{aligned} P_1 &= z^{-1}(C_2-C_1)S_{2}^{\mathrm {e}} C_2 S_{3}^{\mathrm {e}},\end{aligned}$$
(27)
$$\begin{aligned} P_2 &= -z^{-1} C_2 S_{3}^{\mathrm {e}},\end{aligned}$$
(28)
$$\begin{aligned} \Delta _{1,2} &= 1,\end{aligned}$$
(29)
$$\begin{aligned} T &= \frac{V_{\mathrm {out}}^{\mathrm {e}}}{V_{\mathrm {in}}^{\mathrm {o}}} = \frac{P_1\Delta _1+P_2\Delta _2}{\Delta } = -2\,z^{-1}. \end{aligned}$$
(30)
This is very straightforward to extend, particularly with an analysis of parasitic capacitances, which eluded most of the hitherto presented SFG methods. For example, if a \(C_p\) is attached to node 2, the only thing that changes is \(S_{2}^{\mathrm {e}}\) in (24):
$$\begin{aligned} S_{2}^{\mathrm {e}}&= \frac{1}{C_1+C_2+C_p}. \end{aligned}$$
(31)
Then (30) can be calculated again:
$$\begin{aligned} T&= -\frac{2C_1+C_p}{C_1+C_p}\cdot z^{-1}. \end{aligned}$$
(32)
As with the continuous-time DPSFG in Sect.  2, every problem could be solved by step-wise source superposition, but changing the order of how the DPSFG is drawn may make an analysis quicker and less error-prone.

4 Main example: the SC integrator

This is already all of the theory, but the strength of the method lies in the systematic application, so it is best exemplified with a simple (but sufficiently complex) SC circuit: the stray-sensitive SC integrator in Fig. 6.
Fig. 6

Schematics of the simple, stray-sensitive SC integrator. The top schematic has all the switches; the centre schematic shows the odd phase 1, and the bottom schematic shows the even phase 2

In the previous section we just numbered all nodes, but now we introduce a technique that makes the node numbers in all phases unique: the nodes are numbered with powers of 2, i.e., \(1,2,4,8,16,\ldots\), in the schematic with switches, Fig. 6 (top). During the derivation of the odd and even schematics in Fig. 6, nodes of the original circuit are connected by closed switches, and the number of such a new node is the sum of the numbers of the nodes connected.

Since the original numbers were powers of 2, the new nodes are guaranteed to have unique numbers and contain local topological information, with the effect that all elastances \(S_i^{\phi }\) with the same i are the same, irrespective of their phase \(\phi\).

4.1 Calculation with charge equations

The circuit in Fig. 6 can now be analysed using charge equations. The capacitor charges are
$$\begin{aligned} Q_1^{\mathrm {o}}&= V_3^{\mathrm {o}} C_1,\quad Q_2^{\mathrm {o}} = \left( V_4^{\mathrm {o}}-V_8^{\mathrm {o}}\right) C_2 \end{aligned}$$
(33)
in the odd phase and
$$\begin{aligned} Q_1^{\mathrm {e}}&= V_6^{\mathrm {e}} C_1,\quad Q_2^{\mathrm {e}} = \left( V_6^{\mathrm {e}}-V_8^{\mathrm {e}}\right) C_2 \end{aligned}$$
(34)
in the even phase, where \(Q_{1,2}\) is the charge on \(C_{1,2}\) with the positive plate of the capacitors indicated in Fig. 6.
The amplifier with gain A works in both phases, giving two equations:
$$\begin{aligned} V_8^{\mathrm {o}} = A\,V_4^{\mathrm {o}},\quad V_8^{\mathrm {e}} = A\,V_6^{\mathrm {e}}. \end{aligned}$$
(35)
Now it is straightforward to write down the charge differences on the capacitors during the phase transitions:
$$\begin{aligned} \Delta Q_1^{\mathrm {e}}&= Q_1^{\mathrm {e}} - z^{-1} Q_1^{\mathrm {o}}, \quad \Delta Q_2^{\mathrm {e}} = Q_2^{\mathrm {e}} - z^{-1} Q_2^{\mathrm {o}}, \end{aligned}$$
(36)
$$\begin{aligned} \Delta Q_1^{\mathrm {o}}&= Q_1^{\mathrm {o}} - z^{-1} Q_1^{\mathrm {e}}, \quad \Delta Q_2^{\mathrm {o}} = Q_2^{\mathrm {o}} - z^{-1} Q_2^{\mathrm {e}}. \end{aligned}$$
(37)
Then there is charge conservation. In each phase, there are nodes without voltage sources on them where no charge can appear or disappear. In the odd phase, this is only node 4, giving the equation
$$\begin{aligned} \Delta Q_2^{\mathrm {o}}&= 0. \end{aligned}$$
(38)
In the even phase, only node 6 has no voltage source attached, giving one more equation:
$$\begin{aligned} \Delta Q_1^{\mathrm {e}}+\Delta Q_2^{\mathrm {e}}&= 0. \end{aligned}$$
(39)
Observe how both \(\Delta Q_1^{\mathrm {e}}\) and \(\Delta Q_2^{\mathrm {e}}\) are on the same side of the equation; this is because both capacitor plates connected to node 6 in the even phase have the same sign on them.
The final step is to specify the input and the output of the circuit:
$$\begin{aligned} V_{\mathrm {in}}^{\mathrm {o}} = V_3^{\mathrm {o}}, \quad V_{\mathrm {out}}^{\mathrm {o}} = V_8^{\mathrm {o}}. \end{aligned}$$
(40)
The equation system (33)–(40) can now be solved for \(V_{\mathrm {out}}^{\mathrm {o}}\):
$$\begin{aligned} \frac{V_{\mathrm {out}}^{\mathrm {o}}}{V_{\mathrm {in}}^{\mathrm {o}}}&= -\frac{A\,C_1 z^{-2}}{(A+1)C_2+C_1 - z^{-2} (A+1) C_2} \nonumber \\&\approx -\frac{C_1}{C_2 }\,\frac{z^{-2}}{1 - z^{-2}}\quad \text {for}\;A\rightarrow \infty . \end{aligned}$$
(41)
Considering that our \(z^{-2}\) means we have one delay from an odd phase to the next odd phase (see “Appendix”), this is the well-known transfer function of the SC integrator (e.g., [15]).

4.2 Calculation with a driving-point signal-flow graph

The same calculation can now be done with signal-flow graphs. In this section we show how to do it systematically. First, auxiliary sources have to be attached to all circuit nodes that do not already have voltage sources on them. These are the nodes 4 and 6 in Fig. 7.
Fig. 7

Schematics from Fig. 6 with aux sources

Second, a signal-flow graph can be prepared, as shown in Fig. 8(a). This graph contains the input and output paths, the amplifying paths, and, in every node where there is an aux source, also an aux-source charge and an elastance path. The elastances are:
$$\begin{aligned} S_4^{\mathrm {o}}&= \frac{1}{C_2} \quad S_6^{\mathrm {e}} = \frac{1}{C_1+C_2}. \end{aligned}$$
(42)
Fig. 8

DPSFG derived from Fig. 7; a shows the first step, b the complete graph

Third, all paths due to all voltage sources can be drawn, leading from Fig. 8(a, b). We will just explain two of these paths. First, let all voltage sources be zero, and then let \(V_8^{\mathrm {o}}\) be switched to its value. Then the charge \(C_2 V_8^{\mathrm {o}}\) will flow into the aux source at node 4, giving a contribution to \(Q_4^{\mathrm {o}}\). This is the path with weight \(C_2\) from \(V_8^{\mathrm {o}}\) to \(Q_4^{\mathrm {o}}\).

However, this is not the only effect \(V_8^{\mathrm {o}}\) will have, because in this step of calculating source superposition, all other voltages are zero, particularly all voltages in the even phase. The capacitor \(C_2\) has now been charged to \(-C_2 V_8^{\mathrm {o}}\) in the odd phase (observe the \(+\) sign on the left plate of \(C_2\) to understand why the charge is negative), and in the even phase it is completely discharged because the voltage is zero on both sides. Therefore the charge \(-C_2 V_8^{\mathrm {o}}\) flows into the aux source at node 6. Since this is after a phase change, we get a path \(-z^{-1}C_2\) from \(V_8^{\mathrm {o}}\) to \(Q_6^{\mathrm {e}}\).

All other missing paths can then be found by applying the same method to \(V_3^{\mathrm {o}}\), \(V_4^{\mathrm {o}}\), \(V_6^{\mathrm {e}}\), and \(V_8^{\mathrm {e}}\), and then the DPSFG is complete.

Finally, it would already be possible to apply Mason’s gain rule, and if our only goal were to get a transfer function as quickly as possible, then we would stop here. However, using one of the graphical simplification methods mentioned in Sect. 2, Fig. 8(b) can readily be re-drawn as Fig. 9. Then a term \(C_2(A+1)\) appears, and it becomes visible in the graph already that \(C_2\) is subject to the Miller effect.
Fig. 9

DPSFG derived from Fig. 8(b) by graphical simplification. In Fig. 8(b), there were two ways to go from \(V_4^{\mathrm {o}}\) to \(Q_6^{\mathrm {e}}\), one had the weight \(z^{-1}C_2\), the other the weight \(A\,z^{-1}C_2\). Their sum is \(z^{-1}C_2(A+1)\), which is the path from \(V_4^{\mathrm {o}}\) to \(Q_6^{\mathrm {e}}\) in this SFG. The same was done for the path from \(V_6^{\mathrm {e}}\) to \(Q_4^{\mathrm {o}}\)

The graph in Fig. 9 has only three loops:
$$\begin{aligned} L_1&= -A\,S_4^{\mathrm {o}}C_2,\quad L_2 = -A\,S_6^{\mathrm {e}}C_2, \end{aligned}$$
(43)
$$\begin{aligned} L_3&= S_4^{\mathrm {o}}z^{-1}C_2(A+1)S_6^{\mathrm {e}}z^{-1}C_2(A+1). \end{aligned}$$
(44)
According to Mason’s gain rule, the graph determinant becomes
$$\begin{aligned} \Delta = 1-L_1-L_2-L_3+L_1L_2. \end{aligned}$$
(45)
Note that the term \(L_1L_3\) does not appear, because Loop 1 and Loop 3 have nodes in common, and the same is true for \(L_2L_3\).
There is one path from \(V_{\mathrm {in}}^{\mathrm {o}}\) to \(V_{\mathrm {out}}^{\mathrm {o}}\),
$$\begin{aligned} P_1 = z^{-1}C_1S_6^{\mathrm {e}}z^{-1}C_2(A+1)S_4^{\mathrm {o}}(-A), \end{aligned}$$
(46)
and since this path touches all three loops, its sub-determinant \(\Delta _1=1\).
With this information, the transfer function of the circuit can be calculated as
$$\begin{aligned} \frac{V_{\mathrm {out}}^{\mathrm {o}}}{V_{\mathrm {in}}^{\mathrm {o}}} = \frac{P_1\Delta _1}{\Delta }, \end{aligned}$$
(47)
which, of course, gives the same result obtained in (41).

As before, calculating the effects of parasitic capacitors would be simple with this method as they would only change the elastance equations (42).

4.3 Comparison of the two methods

This DPSFG method gives a direct, graphical way to draw a graph from a circuit and solve it using Mason’s gain rule. What remains to be shown now is how the two methods relate.

In the classical method, we wrote down charge conservation equations at all nodes where there were no voltage sources. In the DPSFG method, we introduced aux sources to all nodes where there were no voltage sources. So it stands to reason that the SFG branches pertaining to the aux-source nodes should be charge conservation equations, just as they were KCL equations in the continuous-time case.

Proof for (39): First, substitute (36) into (39):
$$\begin{aligned}&Q_1^{\mathrm {e}} - z^{-1} Q_1^{\mathrm {o}} + Q_2^{\mathrm {e}} - z^{-1} Q_2^{\mathrm {o}} =0 \end{aligned}$$
(48)
Now substitute (33) and (34) into (48):
$$\begin{aligned}V_6^{\mathrm {e}} C_1 - z^{-1} V_3^{\mathrm {o}} &C_1 + \left( V_6^{\mathrm {e}}-V_8^{\mathrm {e}}\right) C_2 \nonumber \\&\quad - z^{-1} \left( V_4^{\mathrm {o}}-V_8^{\mathrm {o}}\right) C_2 =0. \end{aligned}$$
(49)
This can be re-ordered as follows:
$$\begin{aligned} V_6^{\mathrm {e}} (C_1+C_2)&= z^{-1} C_1 V_3^{\mathrm {o}} + C_2 V_8^{\mathrm {e}} \nonumber \\&\quad + z^{-1} C_2 V_4^{\mathrm {o}}- z^{-1} C_2 V_8^{\mathrm {o}}. \end{aligned}$$
(50)
Now let us look at Fig. 8(b), at the DPSFG branch from \(Q_6^{\mathrm {e}}\) to \(V_6^{\mathrm {e}}\). It has the weight \(S_6^{\mathrm {e}}\), which corresponds to the equation
$$\begin{aligned} V_6^{\mathrm {e}}=S_6^{\mathrm {e}}Q_6^{\mathrm {e}}. \end{aligned}$$
(51)
Substituting (42) into this and solving for \(Q_6^{\mathrm {e}}\) gives:
$$\begin{aligned} Q_6^{\mathrm {e}}=V_6^{\mathrm {e}}(C_1+C_2). \end{aligned}$$
(52)
This can now be used together with (50) to calculate \(Q_6^{\mathrm {e}}\):
$$\begin{aligned} Q_6^{\mathrm {e}}&= z^{-1} C_1 V_3^{\mathrm {o}} + C_2 V_8^{\mathrm {e}} \nonumber \\&\quad +\,z^{-1} C_2 V_4^{\mathrm {o}}- z^{-1} C_2 V_8^{\mathrm {o}}, \end{aligned}$$
(53)
and it is immediately apparent that this is the equation obtained from adding all branches going into the node \(Q_6^{\mathrm {e}}\) in the DPSFG.

In summary, the connection of an aux source causes the charge conservation equation for this node to appear in the graph. This is why the method will work for any SC circuit operating with voltage settling and charge transfer.

5 Second example: multi-phase SC networks and discrete-time input impedance

The real power of this method lies in the fact that it only uses very basic principles, and therefore can be applied to any switched-capacitor circuit that works with settling and charge transfer. We will now demonstrate this using the simulated inductor in Fig. 10. This circuit does not only have four phases, but it requires the calculation of the input charge difference \(\Delta Q_{\mathrm {in}}\) that the input source \(V_{\mathrm {in}}\) has to provide.
Fig. 10

A four-phase SC circuit: the simulated inductor from [16, Fig. 4]

The first step is to draw the circuit in its four phases; we call them a, b, c and d instead of e and o. This is shown in Fig. 11.
Fig. 11

The circuit from Fig. 10 shown in its four phases (called a, b, c, and d, from top to bottom)

Drawing the DPSFG can be done as before: first, we draw the graph in Fig. 12(a) by observing the source superposition theorem in all four phases individually, and then we obtain Fig. 12(b) by inserting the paths showing charge transfer between the phases.
Fig. 12

The DPSFGs derived from Fig. 11. Graph a shows the portions of each graph derived from the individual phases, b adds the paths for charge transfer between phases and for calculating the input charge according to (58)

The elastances on the branches of Fig. 12 are:
$$\begin{aligned} S_4^{\mathrm {a}} = S_4^{\mathrm {c}} = S_4^{\mathrm {d}}&= (C_2)^{-1}, \end{aligned}$$
(54)
$$\begin{aligned} S_6^{\mathrm {b}}&= (C_0+C_2)^{-1},\end{aligned}$$
(55)
$$\begin{aligned} S_{16}^{\mathrm {b}} = S_{16}^{\mathrm {c}}&= (C_1)^{-1},\end{aligned}$$
(56)
$$\begin{aligned} S_{18}^{\mathrm {d}}&= (C_0+C_1)^{-1}, \end{aligned}$$
(57)
and as explained in Sect. 4, all elastances with the same index number are the same, even if they are in different phases.
Two more things should be noticed when going from Fig. 12(a, b): first, we have applied the simplification demonstrated in Fig. 9, which is why the integrating capacitor \(C_2\) gives rise to four paths with the weight \((1+A)z^{-1}C_2\). Second, the input charge \(\Delta Q_{\mathrm {in}}\) has two contributions. At the beginning of phase a, the charge of \(C_0\) is \(C_0V_{18}^{\mathrm {d}}\). At the end it is \(C_0V_{2}^{\mathrm {a}}\). The charge \(\Delta Q_{\mathrm {in}}\) that has to be supplied by the voltage source is therefore
$$\begin{aligned} \Delta Q_{\mathrm {in}} = C_0V_{2}^{\mathrm {a}}-z^{-1}C_0V_{18}^{\mathrm {d}}. \end{aligned}$$
(58)
This gives the two branches from \(V_{18}^{\mathrm {d}}\) and from \(V_{2}^{\mathrm {a}}\) to \(\Delta Q_{\mathrm {in}}\), and the signal-flow graph is complete.
At this point we can evaluate Mason’s gain rule: There is one loop each in each of the four phases, and one big loop going through everything:
$$\begin{aligned} L_1&= S_4^{\mathrm {a}} \, (-A) \, C_2, \end{aligned}$$
(59)
$$\begin{aligned} L_2&= S_6^{\mathrm {b}} \, (-A) \, C_2,\end{aligned}$$
(60)
$$\begin{aligned} L_3&= S_4^{\mathrm {c}} \, (-A) \, C_2,\end{aligned}$$
(61)
$$\begin{aligned} L_4&= S_4^{\mathrm {d}} \, (-A) \, C_2,\end{aligned}$$
(62)
$$\begin{aligned} L_5&= S_4^{\mathrm {a}}\, S_6^{\mathrm {b}}\, S_4^{\mathrm {c}}\, S_4^{\mathrm {d}}\, \left( (1+A) z^{-1} C_2\right) ^4 . \end{aligned}$$
(63)
The graph determinant is:
$$\begin{aligned} \Delta&= 1 - L_1 - L_2 - L_3 - L_4 - L_5 \nonumber \\&\quad +\,L_1L_2 + L_1L_3 + L_1L_4 + L_2L_3 + L_2L_4 + L_3L_4 \nonumber \\&\quad -\,L_1L_2L_3 - L_1L_2L_4 - L_2L_3L_3 \nonumber \\&\quad +\, L_1L_2L_3L_4. \end{aligned}$$
(64)
There are three forward paths,
$$\begin{aligned} P_1&= C_0, \end{aligned}$$
(65)
$$\begin{aligned} P_2&= z^{-1}C_0\,S_6^{\mathrm {b}}\,\left( (1+A) z^{-1} C_2\right) \, S_4^{\mathrm {c}}\,(-A)\nonumber \\&\quad \cdot \,z^{-1}C_0\,S_{18}^{\mathrm {d}}\, \left( -z^{-1}C_0\right) , \end{aligned}$$
(66)
$$\begin{aligned} P_3&= z^{-1}C_0\,S_6^{\mathrm {b}}\,S_4^{\mathrm {c}}\,S_4^{\mathrm {d}}\, S_4^{\mathrm {a}}\,\left( (1+A) z^{-1} C_2\right) ^3\,(-A)\nonumber \\&\quad \cdot \,z^{-1}C_1\,S_{16}^{\mathrm {b}}\,S_{16}^{\mathrm {c}} \,S_{18}^{\mathrm {d}}\,\left( z^{-1}C_1\right) ^2\, \left( -z^{-1}C_0\right) , \end{aligned}$$
(67)
with the respective sub-determinants
$$\begin{aligned} \Delta _1&= \Delta , \end{aligned}$$
(68)
$$\begin{aligned} \Delta _2&= 1-L_1-L_4+L_1L_4,\end{aligned}$$
(69)
$$\begin{aligned} \Delta _3&= 1. \end{aligned}$$
(70)
Now it is possible to compute the discrete-time input admittance, which has the unit \(\hbox {F}\), as follows:
$$\begin{aligned} Y_{\mathrm {in}} = \frac{\Delta Q_{\mathrm {in}}}{V_{\mathrm {in}}}&= \frac{P_1\Delta _1+P_2\Delta _2+P_3\Delta _3}{\Delta } \end{aligned}$$
(71)
$$\begin{aligned}&\quad\quad= P_1 + \frac{P_2\Delta _2+P_3\Delta _3}{\Delta }, \end{aligned}$$
(72)
the latter line comes from the fact that \(\Delta _1 = \Delta\).
Substituting (54) to (70) into (72) gives a rather complicated expression, which we will not reproduce here. In [16], the whole calculation is made for \(A\rightarrow \infty\); if we do this as well, we get
$$\begin{aligned} Y_{\mathrm {in}} = C_0 \left[ 1+\frac{C_0\,z^{-4}}{C_2\left( C_0+C_1\right) } \, \frac{C_0+C_1\,z^{-4}}{1-z^{-4}} \right] , \end{aligned}$$
(73)
which is the same as Eq. (15) in [16]. This acts like a discrete-time simulated inductor for a specific choice of capacitor ratios: Inserting \(C_1=C_0/3\) and \(C_2=C_0/4\) into (73) gives
$$\begin{aligned} Y_{\mathrm {in}} = C_0\,\frac{\left( 1+z^{-4}\right) ^2}{1-z^{-4}}. \end{aligned}$$
(74)
Since this is a four-phase system which only samples the input at phase 1, this corresponds to
$$\begin{aligned} Y_{\mathrm {in}} = C_0\,\frac{\left( 1+z^{-1}\right) ^2}{1-z^{-1}}. \end{aligned}$$
(75)
relative to phase one (see “Appendix”). As expected for an inductance, the admittance has one pole at \(z=1\) (which corresponds to \(f=0\)).

6 When Mason is too difficult...

The example in the previous section resulted in a very complicated and tedious evaluation of Mason’s gain rule. Clearly, this example is at the border of what is reasonably calculatable by hand.

Note, however, that this only concerns Mason’s rule. We can still use the DPSFG method to obtain a correct graph that corresponds to the circuit diagram (which makes it easily reviewable), but then use a computer algebra tool (Mathematica, Python/NumPy/SciPy,...) to actually evaluate the equation system.

Such a computation entails listing the dependent variables, listing all equations (one per node), and then solving the equations and substituting the elastances.

This can easily be done for the graph in Fig. 12, but we will show the script for the graph in Fig. 9 such that it is more instructive to the reader. In Mathematica1 notation, this would be:

A brief explanation: In Mathematica, = is an assignment, == an equality, -> a substitution rule, and the operator /. performs substitutions. The solution sols consists of one substitution rule for every dependent variable. Therefore, the last line calculates the transfer function voo/vio, substitutes the solution for voo and then the elastances elast, takes the \(\lim _{A\rightarrow \infty }\;\), and finally simplifies. The result of this code is:

This is evidently the same as (41).

7 Conclusions

In this paper, we have adapted the driving-point signal-flow graphs (SFGs) to switched-capacitor circuits by one main modification: we have exchanged the zero-current auxiliary source by a zero-charge aux source. This let the driving-point impedances become driving-point elastances.

We have demonstrated the application of the method by examples, in which we also showed a few tricks helping simplify the analysis even further, and have shown by argument that this method is applicable to any SC circuit relying on charge transfer just as the original method is applicable to any linear continuous-time circuit.

Therefore, we have unified the SFG analysis methodology for continuous-time and SC circuits. Our method only requires that the users remember Mason’s gain rule and understand source superposition and the aux source. Written material like tables of partial transfer functions, equivalent circuits, etc., are unnecessary. In this respect our method is unique among graph-based SC analysis methods.

Of course, the same analysis can be done by deriving and solving charge equations, which would give the same symbolic results with fewer steps and more quickly using a computer algebra tool. The graph method, however, maintains causal relationships and makes them visible, and when studying and comparing different SC structures, this insight is often worth the additional effort.

While the last example gave a very complicated graph determinant and is at the limit of what can be done by hand (in fact, we, the authors, evaluated Mason’s rule using Mathematica to be sure we do not make stupid mistakes), the one-to-one correspondence makes it straightforward to review a drawn SFG versus its circuit. It is uncommon with this method that an equation is omitted, and near impossible to introduce redundant equations, which is something that everyone who has analyzed circuits by hand using equations knows all too well.

Using Mason’s gain rule to derive transfer functions can give more insight into a circuit, but if evaluating Mason’s rule becomes too complicated, then calculating transfer functions from a signal-flow graph can also be done directly by entering the euqations into a computer algebra tool.

Footnotes

  1. 1.

    Note that at the time we write this paper, Mathematica is available on the cheap Raspberry Pi computers for free, and calculations such as the ones described here do not take much computation time even on such a comparatively slow computer.

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Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Authors and Affiliations

  1. 1.Institute of MicroelectronicsUniversity of Applied Sciences and Arts NW SwitzerlandWindischSwitzerland

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