Advertisement

Design and simulation of nanoelectronic data transfer system with an emphasis on reliability and stability analysis

  • Arpita GhoshEmail author
  • Amit Jain
  • Subir Kumar Sarkar
Article
  • 31 Downloads

Abstract

This work represents the implementation of a data transfer system using single electron threshold logic based approach. The power consumption of the complete system is 239.2 pW. The complete implementation of the design along with the simulation results of different individual stages is presented in this work. The reliability of the system is one of the main concerns as the background charge fluctuation affects the overall system performance. Considering the background charge to be uniformly and normally distributed the variation of the percentage of reliability along with the variation factor for different type of distributions has been plotted and explained. The stability issue of the circuit has also been discussed using stability plots.

Keywords

2:4 decoder Data transfer system Multiplexer Parallel in parallel out register Reliability analysis SIMON Single electron transistor Stability plot Threshold logic 

References

  1. 1.
    Tau, Y., Buchanan, D. A., Chen, W., Frank, D., Ismail, K., Lo, S., et al. (1997). CMOS scaling into the nanometer regime. Proceeding of the IEEE, 85, 486–504.CrossRefGoogle Scholar
  2. 2.
    Hosseini, V. K., Ahmadi, M. T., Afrang, S., & Ismail, R. (2018). Analysis and simulation of coulomb blockade and coulomb diamonds in fullerene single electron transistors. Journal of Nanoelectronics and Optoelectronics, 13(1), 138–143.CrossRefGoogle Scholar
  3. 3.
    Chaudhari, J. R., & Gautam, D. K. (2018). Analysis of encoder and decoder by using multiple valued (MV) hybrid SETMOS. Silicon.  https://doi.org/10.1007/s12633-017-9741-8.Google Scholar
  4. 4.
    Ghosh, A., Jain, A., & Sarkar, S. K. (2017). Small-signal model for the single-electron transistor: Part I. Journal of Computational Electronics, 16(2), 296–306.CrossRefGoogle Scholar
  5. 5.
    Amat, E., Bausells, J., & Maurano, F. P. (2017). Exploring the influence of variability on single-electron transistors into SET-based circuits. IEEE Xplore: IEEE Transactions on Electron Devices, 64(12), 5172–5180.Google Scholar
  6. 6.
    Jeng, E. S., Chou, S. W., Vhen, H. X., & Chiang, H. L. (2017). Chip implementation of supervised neural network using single-transistor synapses. Microelectronics Journal, 66, 76–83.CrossRefGoogle Scholar
  7. 7.
    Hu, C., Cotofana, S. D., & Jiang, J. (2004). Single-electron tunneling transistor implementation of periodic symmetric functions. IEEE Transactions Circuits and Systems-II: Express Briefs, 51, 593–597.CrossRefGoogle Scholar
  8. 8.
    Droulers, G., Eccofey, S., Piero-Ladiriere, M., & Drouin, D. (2017). Metallic single electron transistors: Impact of parasitic capacitances on small circuits. IEEE Transactions on Electron Devices, 64(12), 5202–5208.CrossRefGoogle Scholar
  9. 9.
    Meenderinck, C., & Cotofana, S. (2007). Computing division using single-electron tunneling technology. IEEE Transactions on Nanotechnology, 6(4), 451–459.CrossRefGoogle Scholar
  10. 10.
    Agarwal, P. B., & Kumar, A. (2011). Design and simulation of octal-to-binary encoder using capacitive single-electron transistors (C-SETs). Microelectronics Journal, 42(1), 96–100.CrossRefGoogle Scholar
  11. 11.
    Abutaleb, M. M. (2013). Design and simulation of novel TLG–SET based RAM cell designs. Microelectronics Journal, 44(6), 504–510.CrossRefGoogle Scholar
  12. 12.
    Lageweg, C., Cotofana, S., & Vassiliadis, S. (2006). Evaluation methodology for single electron encoded threshold logic gates. In M. Glesner, R. Reis, L. Indrusiak, V. Mooney, & H. Eveking (Eds.), IFIP international federation for information processing (Vol. 200, pp. 247–262)., VLSI-SOC: From systems to chips Boston: Springer.Google Scholar
  13. 13.
    Bahrepour, D., & Sharifi, M. J. (2013). A novel high speed full adder based on linear threshold gate and its application to a 4-2 compressor. Arabian Journal for Science and Engineering, 38(11), 3041–3050.CrossRefGoogle Scholar
  14. 14.
    Jain, A., Ghosh, A., Singh, N. B., & Sarkar, S. K. (2015). Implementation aspects of logic functions using single electron threshold logic gates and hybrid SET-MOS circuits. IETE Journal of Research, 62(4), 479–487.  https://doi.org/10.1080/03772063.2015.1086703.CrossRefGoogle Scholar
  15. 15.
    Lageweg, C. R., Cotofana, S. D., & Vassiliadis, S. (2002). Static buffered SET based logic gates. In 2nd IEEE conference on nanotechnology (NANO) (pp. 491–494).Google Scholar
  16. 16.
    Wasshuber, C. (1997). SIMON-A simulator for single-electron tunnel devices and circuits. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 16, 937–944.CrossRefGoogle Scholar
  17. 17.
    Tsiolakis, T., Konofaos, N., & Alexiou, G Ph. (2008). Design, simulation and performance evaluation of a single-electron 2-4 decoder. Microelectronics Journal, 39, 1613–1621.CrossRefGoogle Scholar
  18. 18.
    Shin, M., Lee, S., & Park, K. W. (2001). Stability diagram of coupled single-electron transistors. Journal of the Korean Physical Society, 39(3), 581–585.Google Scholar
  19. 19.
    Ghosh, A., Jain, A., Singh, N. B., & Sarkar, S. K. (2015). Stability aspects of single electron threshold logic based 4 bit carry look ahead adder. In Proceedings of the 2015 third international conference on computer, communication, control and information technology (C3IT), Hooghly (pp. 1–4).  https://doi.org/10.1109/c3it.2015.7060138.
  20. 20.
    Chen, C., & Mi, J. (2006). Parameter selection for single electron threshold logic with reliability analysis. In Proceedings of the IEEE International Conference on Nanotechnology, Cincinnati, OH, Jul. 2006 (Vol. 1, pp. 371–374).Google Scholar
  21. 21.
    Ghosh, A., Jain, A., Singh, N. B., & Sarkar, S. K. (2015). Reliability aspects and performance analysis of single electron threshold logic based programmable logic array. Journal of Computational and Theoretical Nanoscience, ASP, 12(9), 2405–2414.CrossRefGoogle Scholar
  22. 22.
    Chen, C., & Mao, Y. (2008). A statistical reliability model for single-electron threshold logic. IEEE Transactions on Electron Devices, 55(6), 1547–1553.CrossRefGoogle Scholar
  23. 23.
    Mahapatra, S., Ionescu, A. M., Banerjee, K., & Declerq, M. J. (2002). Modeling and analysis of power dissipation in single electron logic. In IEDM technical digest, San Francisco, CA (pp. 3236).Google Scholar
  24. 24.
    Durrani, Z. A. K. (2010). Single electron devices and circuits in silicon. London: Imperial College Press.Google Scholar
  25. 25.
    Uchida, K., Koga, J., Ohata, A., & Toriumi, A. (1999). Silicon single-electron tunneling device interfaced with a CMOS inverter. IOP Science & Nanotechnology, 10, 198–200.CrossRefGoogle Scholar
  26. 26.
    Deng, G., & Chen, C. (2013). Binary multiplication using hybrid MOS and multi-gate single-electron transistors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(9), 1573–1582.CrossRefGoogle Scholar
  27. 27.
    Abutaleb, M. M. (2015). A new static differential design style for hybrid SET–CMOS logic circuits. Journal of Computational Electronics, 14(1), 329–340.CrossRefGoogle Scholar
  28. 28.
    Koppinen, P. J., Stewart, M. D., Jr., & Zimmerman, N. M. (2013). Fabrication and electrical characterization of fully CMOS-compatible si single-electron devices. IEEE Transactions on Electron Devices, 60(1), 78–83.CrossRefGoogle Scholar
  29. 29.
    Jana, A., Singh, N. B., Singh, J. K., & Sarkar, S. K. (2013). Design and simulation of hybrid CMOS-SET circuits. Microelectronics Reliability, 53(4), 592–599.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of ECERCC Institute of Information TechnologyKolkataIndia
  2. 2.Department of ECECMR Institute of TechnologyBangaloreIndia
  3. 3.Department of ETCEJadavpur UniversityKolkataIndia

Personalised recommendations