Design and analysis of high-speed split-segmented switched-capacitor DACs

Article

Abstract

In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise are mathematically analyzed and modelled. The design area WCu is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (W, Cu) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.

Keywords

High-speed DACs SC DACs 12-bit split-segmented DACs Linear output driver Wideband wireless communications 

References

  1. 1.
    High Rate Ultra Wideband PHY and MAC Standard. Standard ECMA-368 (2008).Google Scholar
  2. 2.
    WirelessHD Specification v1.1 overview. Standard (2010). http://www.wirelesshd.org/
  3. 3.
    Wu, X., et al. (2008). A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC. IEEE Journal of Solid-State Circuits, 43, 2396–2403.CrossRefGoogle Scholar
  4. 4.
    Lin, C. H., et al. (2009). 12 bit 2.9 GS/s DAC with IM3 < −60 dBc Beyond 1 GHz in 65 nm CMOS. IEEE Journal of Solid-State Circuits, 44, 3285–3293.CrossRefGoogle Scholar
  5. 5.
    Palmers, P., et al. (2010). A 10-Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS. IEEE TCASI, 57, 2870–2879.MathSciNetGoogle Scholar
  6. 6.
    Lin, W.-T., et al. (2014). A 12-bit 40 nm DAC achieving SFDR > 70 dB at 1.6 GS/s and IMD < -61 dB at 2.8 GS/s with DEMDRZ technique. IEEE Journal of Solid-State Circuits, 49, 708–717.CrossRefGoogle Scholar
  7. 7.
    Su, S., et al. (2015). A 12 bit 1 GS/s Dual-Rate Hybrid DAC with an 8 GS/s unrolled pipeline delta-sigma modulator achieving > 75 dB SFDR over the Nyquist Band. IEEE Journal of Solid-State Circuits, 50, 896–907.CrossRefGoogle Scholar
  8. 8.
    Radulov, G. I., et al. (2015). A 28-nm CMOS 7-GS/s 6-bit DAC with dft clock and memory reaching SDFR > 50 dB up to 1 GHz. IEEE Trans. VLSI, 49, 1941–1945.CrossRefGoogle Scholar
  9. 9.
    Olieman, E., et al. (2015). An interleaved full Nyquist high-speed DAC technique”. IEEE Journal of Solid-State Circuits, 50, 704–713.CrossRefGoogle Scholar
  10. 10.
    Manganaro, G., et al. (2004). A Dual 10-b 200-MSPS Pipeline D/A Converter With DLL-Based Clock Synthesizer. IEEE Journal of Solid-State Circuits, 39, 1829–1838.CrossRefGoogle Scholar
  11. 11.
    Daigle, C. et al. (2010). A 12-bit 800-MS/s switched-capacitor DAC with open-loop output driver and digital predistortion. In IEEE Asian Solid-State Circuits Conference, pp. 1–4.Google Scholar
  12. 12.
    Duong, Q.-T., et al. (2014). Design and analysis of high speed capacitive pipeline DACs. Journal of Analog Integrated Circuits and Signal Processing, 80, 359–374.CrossRefGoogle Scholar
  13. 13.
    Daigle, C. (2010). Switched-capacitor DACs using open-loop output drivers and digital predistortion. Ph.D. dissertation.Google Scholar
  14. 14.
    Zhu, Y. M. (1992). Generalized sampling theorem. IEEE TCASII, 39, 587–588.MATHGoogle Scholar
  15. 15.
    Kim, B., et al. (2000). A new linearization technique for MOSFET RF amplifier using multiple gated transistors. IEEE Microwave and Guided Wave Letter, 10(9), 270–273.Google Scholar
  16. 16.
    Leung, B. H. (2002). VLSI for wireless communication. Englewood Cliffs, NJ: Prentice-Hall.Google Scholar
  17. 17.
    Maloberti, F. (2008). Data converters. Berlin: Springer.Google Scholar
  18. 18.
    Plas, G. A. M. V. D., et al. (1999). A 14-bit intrinsic accuracy Q2 random walk CMOS DAC. IEEE Journal of Solid-State Circuits, 34(12), 1708–1718.CrossRefGoogle Scholar
  19. 19.
    Wang, F. J., et al. (1989). A quasipassive CMOS pipeline D/A converter. IEEE Journal of Solid-State Circuits, 24, 1752–1755.CrossRefGoogle Scholar
  20. 20.
    Ding, L., & Mazumder, P. (2003). Simultaneous switching noise analysis using application specific device modeling. IEEE Transactions on VLSI, 11, 1146–1152.CrossRefGoogle Scholar
  21. 21.
    Eo, Y., et al. (2000). New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design. IEEE Transaction on Advanced Packaging, 23, 303–312.CrossRefGoogle Scholar
  22. 22.
    Vemuru, S. R. (1996). “Accurate simultaneous switching noise estimation including velocity-saturation effects”, IEEE Trans. Components, packaging and manufacturing technology, 19, 344–349.CrossRefGoogle Scholar
  23. 23.
    Lee, T. (2004). The design of COS radio-frequency integrated circuits (2nd ed.). Cambridge: Cambridge University Press.Google Scholar
  24. 24.
    Bhide, A., et al. (2015). An 11-GS/s 1.1-GHz bandwidth Interleaved ∆∑DAC for 60-GHz radio in 65-nm CMOS. IEEE Journal of Solid-State Circuits, 50, 2306–2318.CrossRefGoogle Scholar
  25. 25.
    Tokumaru, M. et al. (2009). A 14.6th-order 3.456 GHz transmit baseband filter in 110 nm CMOS for milimeter-wave communication systems. In IEEE CICC, pp. 175–178.Google Scholar
  26. 26.
    Yuriy, M. G., et al. (2011). A 56GS/s 6b DAC in 65 nm CMOS with 256x 6b memory. ISSC, 10, 194–195.Google Scholar
  27. 27.
    Wakimoto, T., et al. (2001). Statistical analysis on the effect of capacitance mismatch in a high-resolution successive-approximation ADC. IEEJ Transactions on Electrical and Electronic Engineering, 6, s89–s93.CrossRefGoogle Scholar
  28. 28.
    Balasubramanian, S., Patel, V. J., & Khalil, W. (2014). Current and emerging trends in the design of digital-to-analog converters. In P. Carbone, S. Kiaei & F. Xu (Eds.), Design, modeling and testing of data converters, pp. 83–116. Springer: Berlin, HeidelbergCrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2017

Authors and Affiliations

  1. 1.Department of Electrical EngineeringLinköping UniversityLinköpingSweden

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