LC-VCOs using spiral inductors with single- and dual-layer patterned floating shields: a comparative study

  • Chee Cheow Lim
  • Harikrishnan RamiahEmail author
  • Jun Yin
  • Pui-In Mak
  • Rui P. Martins
Mixed Signal Letter


This letter studies and compares class-B VCOs using spiral inductors with the proposed dual-layer patterned floating shield (DL-PFS) and conventional single-layer patterned floating shield (SL-PFS). The proposed DL-PFS technique utilizes two lowest metal layers to effectively reduce the capacitive induced current to the substrate in an on-chip spiral inductor, thereby boosts its Q-factor by 40% when compared with the conventional SL-PFS approach. We fabricated, as a proof of concept, the class-B LC-VCOs using the DL-PFS and SL-PFS in 0.13 µm CMOS. Operating at 10 GHz, the VCO with the DL-PFS inductor measures a 3.6 dB phase noise (PN) improvement at the same power consumption of 2.12 mW. Specifically, the VCO with DL-PFS inductor is tunable from 9.3-to-10.1 GHz and measured PN at 10 GHz is −132.5 dBc/Hz at 10 MHz offset while consuming 2.12 mW at the lowest 0.6 V supply. The achieved figure-of-merit (187.4 dBc/Hz@1 MHz offset) compares favorably with the recent state-of-the-art.


Inductor Patterned floating shield Substrate CMOS VCO 



This work was supported by Motorola Foundation Scholarship (PV001-2014) and the University of Macau (MYRG2015-00097-AMSV).


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Copyright information

© Springer Science+Business Media New York 2017

Authors and Affiliations

  • Chee Cheow Lim
    • 1
  • Harikrishnan Ramiah
    • 1
    Email author
  • Jun Yin
    • 2
  • Pui-In Mak
    • 2
  • Rui P. Martins
    • 2
    • 3
  1. 1.University of MalayaKuala LumpurMalaysia
  2. 2.State-Key Laboratory of Analog & Mixed-Signal VLSI, and Faculty of Science & Technology, Department of Electrical and Computer EngineeringUniversity of MacauMacaoChina
  3. 3.Instituto Superior TécnicoUniversidade de LisboaLisboaPortugal

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