Analog Integrated Circuits and Signal Processing

, Volume 90, Issue 2, pp 321–331 | Cite as

A low power reconfigurable multi-mode continuous time Delta Sigma modulator for seven different mobile standards with VCO-based quantizer

Article
  • 179 Downloads

Abstract

In this research a novel low power multi-mode continuous time Delta Sigma modulator was designed to be compatible with many mobile wireless standards. This modulator has a reconfigurable structure to adapt to various standards from 0.2 to 20 MHz. The designed modulator uses a VCO-based quantizer not only for lowering power consumption, but also for reducing the required chip area. The presented modulator can function with up to third order of noise shaping, or in a low power mode in which the loop filter is disabled and only the VCO-based quantizer is used. The proposed modulator was implemented and simulated in transistor level in 180 nm technology. This modulator can digitize at least seven standards (LTE (20 MHz)/WLAN/LTE (9 MHz)/WCDMA/UMTS/Bluetooth/GSM) with a favorable dynamic range (65–89 dB) and power consumption (9.1 mW–670 μW).

Keywords

Delta Sigma modulator Multi-mode ADC VCO-based quantizer Multi-standard receiver 

References

  1. 1.
    Li, X., & Ismail, M. (2002). Multi-standard CMOS wireless receivers: Analysis and design (Vol. 675). New York: Springer Science & Business Media.Google Scholar
  2. 2.
    Gielen, G., & Goris, E. (2005). Reconfigurable front-end architectures and A/D converters for flexible wireless transceivers for 4G radios. In ETW’05. 2005 IEEE 7th CAS symposium on emerging technologies: circuits and systems for 4G mobile wireless communications, 2005, IEEE.Google Scholar
  3. 3.
    Van Veldhoven, R. H. (2003). A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver. IEEE Journal of Solid-State Circuits, 38(12), 2069–2076.CrossRefGoogle Scholar
  4. 4.
    Rusu, A., et al. (2006). A triple-mode sigma-delta modulator for multi-standard wireless radio receivers. Analog Integrated Circuits and Signal Processing, 47(2), 113–124.CrossRefGoogle Scholar
  5. 5.
    Ouzounov, S., et al. (2007). A 1.2 V 121-mode CT ΔΣ modulator for wireless receivers in 90 nm CMOS. In 2007 IEEE international solid-state circuits conference. Digest of Technical Papers.Google Scholar
  6. 6.
    Morgado, A., et al. (2010). A 0.13 μm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications. Microelectronics Journal, 41(5), 277–290.CrossRefGoogle Scholar
  7. 7.
    Crombez, P., et al. (2010). A single-bit 500 kHz–10 MHz multimode power-performance scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm digital CMOS. IEEE Journal of Solid-State Circuits, 45(6), 1159–1171.CrossRefGoogle Scholar
  8. 8.
    Jose, B. R., Mathew, J., & Mythili, P. (2011). A multi-mode sigma-delta ADC for GSM/WCDMA/WLAN applications. Journal of Signal Processing Systems, 62(2), 117–130.CrossRefGoogle Scholar
  9. 9.
    Honarparvar, M., & Aghdam, E. N. (2014). Reconfigurable hybrid CT/DT delta-sigma modulator with op-amp sharing technique dedicated to multi mode receivers. Analog Integrated Circuits and Signal Processing, 79(2), 413–426.CrossRefGoogle Scholar
  10. 10.
    Dörrer, L., et al. (2005). A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS. IEEE Journal of Solid-State Circuits, 40(12), 2416–2427.CrossRefGoogle Scholar
  11. 11.
    Rajaee, O., & Moon, U. K. (2008). Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer. In ISCAS 2008. IEEE international symposium on circuits and systems, 2008, IEEE.Google Scholar
  12. 12.
    Corporales, L. H., et al. (2009). A 1.2-MHz 10-bit continuous-time sigma-delta ADC using a time encoding quantizer. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(1), 16–20.CrossRefGoogle Scholar
  13. 13.
    Ye, Y., et al. (2012). A 120 dB SNDR audio sigma-delta modulator with an asynchronous SAR quantizer. In: 2012 IEEE international symposium on circuits and systems (ISCAS), IEEE.Google Scholar
  14. 14.
    Straayer, M. Z., & Perrott, M. H. (2007). A 10-bit 20 MHz 38 mW 950 MHz CT ΣΑ ADC with a 5-bit noise-shaping VCO-based quantizer and DEM circuit in 0.13 u CMOS.Google Scholar
  15. 15.
    Yoder, S., Ismail, M., & Khalil, W. (2011). VCO-based quantizer. In VCO-based quantizers using frequency-to-digital and time-to-digital converters (pp. 9–29). Springer.Google Scholar
  16. 16.
    Lee, K., Yoon, Y., & Sun, N. (2013). A 10 MHz-BW, 5.6 mW, 70 dB SNDR ΔΣ ADC using VCO-based integrators with intrinsic DEM. In 2013 IEEE international symposium on circuits and systems (ISCAS), IEEE.Google Scholar
  17. 17.
    Prabha, P., et al. (2015). A highly digital VCO-based ADC architecture for current sensing applications. IEEE Journal of Solid-State Circuits, 50(8), 1785–1795.CrossRefGoogle Scholar
  18. 18.
    Straayer, M. Z., & Perrott, M. H. (2008). A 12-bit, 10-MHz bandwidth, continuous-time ADC with a 5-bit, 950-MS/s VCO-based quantizer. IEEE Journal of Solid-State Circuits, 43(4), 805–814.CrossRefGoogle Scholar
  19. 19.
    Gaber, W. M., et al. (2010). Systematic design of continuous-time ΣΔ modulator with VCO-based quantizer. In Proceedings of 2010 IEEE international symposium on circuits and systems (ISCAS), IEEE.Google Scholar
  20. 20.
    Chen, X., et al. (2007). A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications. In Custom integrated circuits conference, 2007. CICC’07. IEEE, IEEE.Google Scholar
  21. 21.
    Morgado, A., del Río, R., & José, M. (2011). Nanometer CMOS sigma-delta modulators for software defined radio. New York: Springer Science & Business Media.Google Scholar
  22. 22.
    Gaggl, R. (2012). Delta-sigma A/D-converters: Practical design for communication systems. New York: Springer Science & Business Media.Google Scholar
  23. 23.
    Schreier, R. (2011). The delta-sigma toolbox, analog devices, release 7.4, also known as “DELSIG”.Google Scholar
  24. 24.
    Gerfers, F., & Ortmanns, M. (2006). Continuous-time sigma-delta A/D conversion: Fundamentals, performance limits and robust implementations (Vol. 21). New York: Springer Science & Business Media.Google Scholar
  25. 25.
    Pavan, S. (2008). Excess loop delay compensation in continuous-time delta-sigma modulators. IEEE Transactions on Circuits and Systems II: Express Briefs, 55(11), 1119–1123.CrossRefGoogle Scholar
  26. 26.
    Mitteregger, G., et al. (2006). A 20-mW 640-MHz CMOS continuous-time ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB. IEEE Journal of Solid-State Circuits, 41(12), 2641–2649.CrossRefGoogle Scholar
  27. 27.
    Razavi, B. (2016). Design of analog CMOS integrated circuits (2nd ed.). New York: McGraw-Hill.Google Scholar

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  1. 1.Integrated Circuits Design Laboratory, Faculty of Electrical EngineeringSahand University of TechnologyTabrizIran

Personalised recommendations