# A pipelined SAR ADC with gain-stage based on capacitive charge pump

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## Abstract

This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-µm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 µW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR >75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm^{2}.

### Keywords

Capacitive charge pump Two-stage pipelined SAR ADC OTA Switch capacitor integrator## 1 Introduction

Wireless sensor networks are employed in many applications, such as monitoring bio-potential signals, environmental information and interactive multimedia. These applications require high-resolution (>12 bits), low-speed (several kS/s) analog-to-digital converters (ADCs) [1]. Such sensor nodes are usually powered by batteries or energy-harvesting sources [2, 3] hence low power consumption is primary for the constituent ADCs. Normally, tens or hundreds of autonomously powered sensor nodes are utilized to capture and transmit data to the central processor. Hence it is profitable to fabricate the relevant electronics, such as the ADCs, in a low-cost standard CMOS process.

The successive approximation register analog-to-digital converters (SAR ADCs) can provide highly power efficiency solution at moderate resolutions, but achieving a SAR ADC with effective number of bits (ENOB) beyond 12 bits shows enormous challenges due to the influence from comparator noise and capacitor mis-matching [4, 5, 6]. The SAR-assisted pipeline ADC is an energy-efficient architecture for high resolution [7]. Such architecture consists of two independent sub-SAR ADCs coupled by a gain-stage. The need of a high-accuracy comparator can be obviated by incorporating a SAR ADC as the sub-ADC in the pipeline stage. However, an additional gain-stage is inevitable to amplify the residue signal. Normally, the switch capacitor (SC) integrator is the primary choice to realize the gain-stage, but a high-gain operational transconductance amplifier (OTA) is necessary to amplify the residue with sufficient accuracy. Since the open-loop DC gain requirement of OTA grows exponentially with the total resolution of the ADC, the design of high-gain OTA is a major challenge for implementing high-resolution pipelined SAR ADC. Meanwhile, as shown in [7, 8, 9], the high gain OTA is always a power-hungry block. So, a lower-power alternative way, such as the dynamic amplifier [10, 11], which allows to switch off the OTA during the reset phase but still needs a high open-loop DC gain. In [12], an open-loop amplifier as the gain stage was offered. Although the open-loop solution shows a low DC gain, this voltage gain will be deeply influenced by the process variation. So the extra calibration technique is inevitable.

To overcome the high DC gain requirement, in this paper, we employ the design, analysis and implementation of a 14-bit, tunable bandwidth two-stage pipelined SAR ADC in 0.35-µm CMOS process which uses a three-stage capacitive charge pump (CCP) as the gain-stage instead of using SC integrator. Since the basic CCP cell can provide a gain of 2 [13], m-stage CCP can be connected in series to achieve a gain of \(2^m\). Combining the gain reduction solution as shown in [14], three-stage CCP was utilized to achieve a stage gain of 8. Since the gain reduction solution requires increased sampling capacitance for the second stage sub-ADC to compensate for the reduced signal swing [8], the attenuation DAC [15] was chosen to alleviate the increased capacitance requirement in the second stage. The segmented capacitive array DAC [16] was implemented in the first stage which meets the targeted static linearity with a lower unit capacitance. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at a sampling rate of 200 kS/s while consuming 7.68 and 96 µW, respectively.

This paper is organized as follows. Section 2 introduces the proposed pipelined SAR ADC architecture and the operating sequence. Section 3 describes the details of circuit implementation. The measurement results are presented in Sect. 4, followed by the conclusions in Sect. 5.

## 2 Architecture of the proposed two-stage pipelined SAR ADC

*N*and also the matching constraints necessitate large unit capacitor in the capacitive array which entails large power consumption and chip area. For the segmented DAC with a segmentation degree

*k*, the unit capacitor value is \(2^{k-1}\) times lower than the unit capacitor for the conventional binary-weighted DAC in order to meet the same targeted static linearity [17]. Hence the SAR ADC with segmented binary-weighted capacitive DAC serves as the first stage in order to relax the unit capacitor value and the active chip area. The multi-stage CCP works as the gain-stage to amplify the residue signal with a inter-stage gain of \(2^{m}\) where the \(m=N_1-r\) and

*r*is the gain reduction factor [14]. Since the basic CCP cell applies an ideal gain of 2 [13], \(N_1-r\) stages are necessary to achieve a gain of \(2^{N_1-r}\). The inter-stage gain is reduced by \(2^r\) times, which means an extra capacitor \(C_x=(2^{r-1}-1) C_{tot2}\) is required for the second stage DAC [14] to compensate for the reduced signal swing where the \(C_{tot2}\) represents the total capacitance of second DAC. So the SAR ADC with split binary-weight capacitive DAC is chosen to alleviate the increased capacitance requirement in the second stage.

## 3 Proposed pipelined SAR ADC architecture implementation

### 3.1 Multi-stage CCP analysis and implementation

The multi-stage CCP architecture is shown in Fig. 1, consisting of several basic charge pump cell [13]. For each cell, it supplies a gain of 2. Thus, the multi-stage CCP could achieve a gain of \(2^m\) ideally. In this architecture, the only active circuitry is the unity gain buffer with a capacitive load of \(C_m\). Proper choice of the \(C_m\) is crucial for keeping the noise level below the corresponding quantization noise. Meanwhile the choice of the stage number *m* is also elaborated upon in this section.

#### 3.1.1 Noise analysis

*k*is the Boltzmann constant and

*T*is the absolute temperature.

#### 3.1.2 Gain requirement and power analysis

*r*and \({\varDelta }e=\frac{1}{\beta A}=\frac{1}{2^{N-N_1}}\) is the gain error caused by the finite open-loop DC gain of the OTA [14]. In order to obtain the same voltage gain by using the CCP architecture,

*m*charge pump stages should be connected in series. The gain of one stage is

*N*is total resolution of ADC , \(V_{FS}\) is the full-scale range of the ADC and

*G*is the voltage gain. For a MOS transistor in strong inversion, the parameter \(V_{eff}=(V_{gs}-V_T)/2\), where \(V_{gs}\) and \(V_T\) are the gate-to-source and threshold voltages respectively [18]. By replacing

*G*with (9), the (14) can be expressed as

*m*-stage CCP is

*m*. To find the influence from larger

*m*,

*N*= 14 and

*N*= 16 was chosen respectively but with the same load capacitance of 3 pF. In practice, the load capacitance increases along with the growth of resolution. From Fig. 6, the OTA power in SC grows exponentially but linearly in CCP. The CCP consumes more power than SC with lower voltage gain due to more unity gain buffers are used. However, the CCP is more power efficient than SC with high voltage gain which shows a power saving potential for designing higher resolution ADC.

In this work, the solution of \(m=3\) has been applied to our 14-bit two-stage pipelined SAR ADC project. It should be pointed out that the main purpose of this work was to verify the overall functionality of the proposed multi-stage capacitive charge pump. Compared to the conventional SC integrator, the CCP gain-stage with a voltage gain of 8 is not power-efficient choice for design of a 14-bit ADC. It remains as a future work to find a low-power analog buffer instead of using the unity-gain OTA. However, Fig. 6 suggests that the presented gain-stage would result in higher power efficiency for higher resolutions, for example for 16-bit ADC with 9-bit in the first-stage.

Unity-gain OTA performance

\(V_{dd}=3.3\,\hbox {V}\) | Unity-gain | ||
---|---|---|---|

Temperature (°C) | Min. | Max. | \(3\sigma\) |

−40 | 0.9963 | 0.9978 | 740.7e−6 |

0 | 0.9968 | 0.9978 | 563.7e−6 |

27 | 0.9968 | 0.9977 | 542.1e−6 |

85 | 0.9967 | 0.9977 | 655.8e−6 |

As the table shows the unity-gain OTA shown in Fig. 3 maintains its gain sufficiently constant. To meet the noise requirement of 14-bit ADC, the \(C_1=3\, \hbox {pF}, C_2=C_3=2\) pF were chosen. Since the input of gain-stage is discrete time, the normal NMOS transistor was used to achieve the switch. It should be mentioned that one more unity gain buffer is needed between the first stage ADC and the input of gain-stage. The gain error caused by this buffer will be compensated by tuning the reference voltage of second ADC.

### 3.2 First-stage SAR ADC implementation

*k*is the segmented degree. Comparing (18) and (19), it is seen that the \(C_{u1}\) for the segmented DAC is \(2^{k-1}\) times lower than that of the conventional DAC. For the poly-insulator-poly (PIP) capacitor in 0.35-µm CMOS process, \(K_\sigma = 0.45\,\%\,\upmu\)m and \(K_c = 0.86\,\hbox {fF}/\upmu \,m^2\). From (18), the minimum mismatch-limited unit PIP capacitor is 163 fF. However, the segmented DAC requires only \(C_{u1} = 40.8\) fF with a segmented degree \(k = 3\). Therefore, it will avail power and active area savings by using a segmented capacitive DAC in the first stage. Here, the minimum mismatch-limited unit capacitance (40.8 fF) is calculated under the assumption that the sampling switch is ideal. In practice, the sampling switch introduces the charge injection and clock feed-through errors which cause additional harmonic distortions. Hence a large unit capacitor of 117.7 fF was required by simulations to achieve the targeted 14-bit ADC performance.

It should be noted that the segmented DAC requires a binary-to-thermometer decoder which lead to extra power consumption and chip area. Larger segmentation degree indicates that the circuit complexity, area occupation and power increase. In [14], the optimal segmentation degree range is \(3\le k \le 5\). In this work, a segmentation degree of \(k = 3\) was chosen for the first stage DAC as a trade-off among lower unit capacitor value, increased circuit complexity and power consumption in the digital logic. Figure 7 shows the schematic of the 3-to-7 binary-to-thermometer decoder required for the unary-weighted 3-bit DAC segment which consists of basic logic gates.

### 3.3 Second-stage SAR ADC implementation

A 8-bit SAR ADC with attenuation capacitor based DAC forms the second-stage sub-ADC. The DAC consists of a 4-bit main-DAC and 4-bit sub-DAC. Because of \(m=3\), the extra capacitor \(C_x=112C_{u2}\) was added into the DAC. As the total capacitance of the second sub-ADC (\(C_{tot2}\)) is also the load capacitance of the gain-stage, an unit PIP capacitor \(C_{u2}\) was chosen as 15.8 fF yielding a \(C_{tot2}=2.0~\hbox {pF}\) to maintain the total input-referred noise of the gain-stage [Eq. (8)] below the quantization noise of 14-bit ADC. Such choice also satisfies the thermal noise and mismatch requirements of the second-stage ADC’s accuracy (11-bit). The SAR logic for the second-stage is similar to that shown in Fig. 8(a) except the reset signal should be connected to \(\phi _{3\_a}\) generated by control logic as shown in Fig. 8(b). Since the accuracy of this stage is 11-bit, a transmission gate was used to design the sampling switch S\(_2\) as shown in Fig. 1. The same dynamic latch comparator topology as in the first stage is used to generate the digital output bits.

## 4 Measurement results

Comparison of the ADC with other high-resolution ADCs

[20] | [21] | [22] | [8] | [9] | [11] | [23] | This work | ||
---|---|---|---|---|---|---|---|---|---|

CMOS (nm) | 350 | 350 | 350 | 130 | 65 | 28 | 65 | 350 | |

Architecture | Pipelined with SC | Pipelined withSC | Pipelined withSC | SAR-assisted withSC | SAR-assisted with Ring amplifier | SAR-assisted with DynamicSC | Nyquist SAR | SAR-assisted with CCP | |

Resolution (bit) | 14 | 14 | 12 | 14 | 13 | 14 | 14 | 14 | |

Calibration | N0 | No | Yes | No | No | Yes | No | No | |

DC gain | 100 dB | – | 60 dB | 86 dB | >80 dB | – | – | 51.8 dB | |

Area (mm | 7.8 | – | 20.6 | 0.24 | 0.054 | 0.137 | 0.28 | 0.589 | |

fs | 75 MS/s | 80 MS/s | 20 MS/s | 30 MS/s | 50 MS/s | 80 Ms/s | 10 kS/s | 20 kS/s | 200 kS/s |

SNDR (dB) | 74 | 74 | 72.5 | 70.8 | 71.5 | 68.0 | 78.1 | 75.6 | 76.1 |

SFDR (dB) | 94 | 100 | 84.4 | 87.8 | 87.0 | 80.7 | 88.5 | 90.9 | 92.7 |

Power | 318 mW | 1200 mW | 56.3 mW | 2.54 mW | 1.0 mW | 1.5 mW | 2.48 µW | 7.68 µW | 96 µW |

FoM (dB) | 154.7 | 149.2 | 155 | 168.5 | 175.5 | 172.3 | 171.1 | 166.7 | 166.3 |

## 5 Conclusion

The three-stage capacitive charge pump as the gain-stage for a 14-bit two-stage pipelined SAR ADC was presented in this work. Due to the tunable bandwidth of CCP, The proposed ADC achieves a SNDR >75 dB upto 260 kHz. Meanwhile the ADC also provides a competitive FoM among related works. By employing the CCP as the gain-stage, the high DC gain OTA in the SC integrator was avoided while also reducing the design complexity. So, we concluded that the multi-stage capacitive charge pump shows an another solution to achieve the function of the gain stage instead of using the SC integrator for the low-speed, two-stage pipelined SAR ADC application.

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