InGaZnO TFT behavioral model for IC design
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This paper presents a behavioral model for amorphous indium–gallium–zinc oxide thin-film transistor using artificial neural network (ANN) based equivalent circuit (EC) approach to predict static and dynamic behavior of the device. In addition, TFT parasitic capacitances (CGS and CGD) characterization through measurements is also reported. In the proposed model, an EC is derived from the device structure, in terms of electrical lumped elements. Each electrical element in the EC is modeled with an ANN. Then these ANNs are connected together as per the EC and implemented in Verilog-A. The proposed model performance is validated by comparing the circuit simulation results with the measured response of a simple common-source amplifier, which has shown 12.2 dB gain, 50 μW power consumption and 85 kHz 3-dB frequency with a power supply of 6 V. The same circuit is tested as an inverter and its response is also presented up to 50 kHz, from both simulations and measurements. These results show that the model is capable of capturing both small and large signal behavior of the device to good accuracy, even including the harmonic distortion of the signal (that emphasizes the nonlinear behavior of the parasitic capacitance), making the model suitable for IC design.
KeywordsEquivalent circuit approach neural models Verilog-A a-IGZO TFT modeling a-IGZO TFT circuits
This work is funded by FEDER funds through the COMPETE 2020 Programme and National Funds through FCT—Portuguese Foundation for Science and Technology under the Project Nos. CMUPT/SIA/0005/2009, UID/CTM/50025/2013 and EXCL/CTM-NAN/0201/2012. The work has also received funding from the European Communities 7th Framework Programme under grant agreement ICT-2013-10-611070 (i-FLEXIS project) and from H2020 program under ICT-03-2014-644631 (ROLL-OUT project).
- 2.Bahubalindruni, G., Tavares, V. G., Barquinha, P., Duarte, C., Martins, R., Fortunato, E., de Oliveira, P. G. (2012). Basic analog circuits with a-GIZO thin-film transistors: Modeling and simulation. In SMACD.Google Scholar
- 5.Chou, K.-I., Hsu, H.-H., Cheng, C.-H., Lee, K.-Y., Li, S.-R., & Chin, A. (2013). A low operating voltage IGZO TFT using LaLuO3 gate dielectric. In IEEE international conference of electron devices and solid-state circuits (EDSSC) (pp. 1–2).Google Scholar
- 9.Meyer, J. E. (1971). Mos models and circuit simulation. RCA Review, 32, 42–63.Google Scholar
- 13.Raiteri, D., Torricelli, F., Myny, K., Nag, M., van der Putten, B., Smits, E., Steudel, S., Tempelaars, K., Tripathi, A., Gelinck, G., van Roermund, A., Cantatore, E. (2012) A 6b 10MS/s current-steering DAC manufactured with amorphous Gallium-Indium-Zinc-Oxide TFTs achieving SFDR > 30dB up to 300 kHz. In ISSCC (pp. 314–316).Google Scholar