Analog Integrated Circuits and Signal Processing

, Volume 85, Issue 2, pp 243–251 | Cite as

Delta–sigma DAC with jitter-shaper-reducing jitter noise

  • Yuki Watanabe
  • Satoshi Saikatsu
  • Michitaka Yoshino
  • Akira Yasuda
Article

Abstract

We present a novel delta–sigma digital-to-analog converter (DSDAC) using a jitter shaper to augment the noise caused by clock jitter. The jitter shaper is designed for a 0.18 µm CMOS and comprises switched capacitor and sample-and-hold circuits. We simulate the DSDAC in MATLAB and design and simulate the complete jitter shaper circuit in SPICE. We predict that the jitter shaper will improve the signal-to-noise ratio by 47.2 dB (MATLAB) up to 24.6 dB (SPICE).

Keywords

D/A converter Delta–sigma modulator Jitter shaper Clock jitter 

References

  1. 1.
    Schreier, R., & Temes, G. C. (2004). An introduction to ΔΣ analog/digital converters (translated from the Japanese by T. Waho & A. Yasuda). Maruzen Co., Ltd.Google Scholar
  2. 2.
    Cherry, J. A., & Snelgrove, W. M. (1999). Clock jitter and quantizer metastability in continuous-time delta–sigma modulators. IEEE Transactions on Circuits and Systems II, 46, 376–389.CrossRefGoogle Scholar
  3. 3.
    Fujimori, I., Nogi, A., & Sugimoto, T. (2000). A multibit delta–sigma audio DAC with 120-dB dynamic range. IEEE Journal of Solid-State Circuits, 35(8), 1066–1073.CrossRefGoogle Scholar
  4. 4.
    Kobayashi, H., Kurosawa, N., Miyauchi, I., Kawakami, S., Kogure, H., Komuro, T., & Sakayori, H. (2003). Timing error analysis in digital-to-analog converter—effects of sampling clock jitter and timing skew (Glitch). In 10th electronic devices and systems conference 2003, Brno, pp. 212–299.Google Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Yuki Watanabe
    • 1
  • Satoshi Saikatsu
    • 1
  • Michitaka Yoshino
    • 1
  • Akira Yasuda
    • 1
  1. 1.Engineering Research CourseHosei UniversityKoganeiJapan

Personalised recommendations