Analog Integrated Circuits and Signal Processing

, Volume 82, Issue 1, pp 197–207 | Cite as

Design of a 3-channel 5 Gb/s/ch deserializer array for high-speed parallel links

  • Chang-Chun Zhang
  • Ming Li
  • Lei-Lei Liu
  • Kui-Ying Yin
  • Gang Bai
  • Yu-Feng Guo
Article
First Online:
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Abstract

A novel 3-channel 5 Gb/s/ch deserializer (DeSER) array is designed and fabricated in a standard 0.18 μm CMOS technology for applications for multi-channel 5 Gb/s/ch parallel links. The 3-channel array consists of one PLL-based DeSER and two DLL-based DeSERs. With a half-rate version of PLL and DLL, the corresponding PFD and PD are improved to realize the function of a 1:2 DeSER implicitly, respectively. The PLL and DLL techniques are combined to deal with the clocking-related issues for the DeSER array, which can come to a good tradeoff between compactness, low power dissipation, reliability, etc. Measured results demonstrate that the DeSER array works properly with no need of reference clock, off-chip tuning, external components, and any specified inter-channel skew. It achieves a power consumption of 380 mW from a single supply of 1.8 V, and a die area of 1,200 μm × 943 μm (including pads) with an average channel width of 250 μm/ch.

Keywords

Deserializer Clock and data recovery Phase locked loop Delay locked loop Inter-channel skew 
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Notes

Acknowledgments

This work was sponsored by the China Postdoctoral Science Foundation (No. 2012M521126), the National Natural Science Foundation of China (No. 61076073), the Provincial Natural Science Foundation of Jiangsu (No. BK20130878, BK2012435, BK20141431), the Jiangsu Province Science and Technology Support Program-Industry Part (No. BE2013130), the Specialized Research Fund for the Doctoral Program of Higher Education (No. 20133223120005, 20133223110003), and the Scientific Research Funds of Nanjing University of Posts and Telecommunications, China (No. NY211016, NY213146).

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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Chang-Chun Zhang
    • 1
  • Ming Li
    • 2
  • Lei-Lei Liu
    • 1
  • Kui-Ying Yin
    • 2
  • Gang Bai
    • 1
  • Yu-Feng Guo
    • 1
  1. 1.College of Electronic Science and EngineeringNanjing University of Posts and TelecommunicationsNanjingChina
  2. 2.Nanjing Research Institute of Electronics TechnologyNanjingChina

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