An integrated 0.38–6 GHz, 9–12 GHz fully differential fractional-N frequency synthesizer for multi-standard reconfigurable MIMO communication application

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Abstract

A wide-band fully differential fractional-N frequency synthesizer for multi-standard application is presented. The single fully differential LC–VCO with 28.5 % tuning rang and a set of dividers, quadrature self-mixer are designed to accomplish the multi-frequency bands with the frequency band from 0.38 to 6 GHz and from 9.0 to 12 GHz. It covers several wireless standards. A novel high isolation multiplexer is presented to achieve the frequency band selection. This chip was implemented with 65 nm CMOS technology and the maximum consumption is 20.05 mA from 1.2 V power supply. It occupies an active area of 1.5 mm2. The measured typical phase noise of the frequency synthesizer is −114.6 dBc/Hz from 1 MHz offset for 4.85 GHz output.

Keywords

Full differential Frequency synthesizer Multi-standard Phase noise Quadrature self-mixer Multiplexer 
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Notes

Acknowledgments

This work was supported by the National Natural Science Foundation of China under Grant No. 60976023, and National Science and Technology Major Project No. 2009ZX03007-001 and No. 2012ZX03004007-002.

References

  1. 1.
    Osmany, S., Herzel, F., & Scheytt, J. (2010). An integrated 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and 20–28 GHz frequency synthesizer for software-defined radio applications. IEEE Journal of Solid-State Circuits, 45(9), 1657–1668.CrossRefGoogle Scholar
  2. 2.
    Badets, F., Camino, L., Rieubon, S., Divel, P., Dedieu, S., & Belot, D. (2005). A multimode GSM/DCS/WCDMA double loop frequency synthesizer. In IEEE Asian Solid-State Circuits Conference (pp. 201–204).Google Scholar
  3. 3.
    Huang, D., Li, W., Zhou, J., Li, N., & Chen, J. (2011). A frequency synthesizer with optimally coupled VCO and harmonic-rejection SSB mixer for multi-standard wireless receiver. IEEE Journal of Solid-State Circuits, 46(6), 1307–1320.CrossRefGoogle Scholar
  4. 4.
    Porret, A.-S., et al. (2000). Design of high-Q varactors for low-power wireless applications using a standard CMOS process. IEEE Journal of Solid-State Circuits, 35(3), 337–345.CrossRefGoogle Scholar
  5. 5.
    Kral, A., Behbahani, F., & Abidi, A. A. (1998). RF-CMOS oscillators with switched tuning. In IEEE Custom Integrated Circuits Conference (pp. 555–558).Google Scholar
  6. 6.
    Cheng, S., Tong, H., Silva-Martinez, J., & Karsilayan, A. (2006). Design and analysis of an ultrahigh-speed glitch-free fully differential charge pump with minimum output current variation and accurate matching. IEEE Transactions on Circuits and Systems, Part II, 53, 843–847.CrossRefGoogle Scholar
  7. 7.
    Vaucher, C. S., Ferencic, I., Locher, M., Sedvallson, S., Voegeli, U., & Wang, Z. (2000). A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology. IEEE Journal of Solid-State Circuits, 35(7), 1039–1045.CrossRefGoogle Scholar
  8. 8.
    Yang, Y.-C., Yu, S.-A., Liu, Y.-H., Wang, T., & Lu, S.-S. (2006). A quantization noise suppression technique for delta sigma fractional-N frequency synthesizers. IEEE Journal of Solid-State Circuits, 41(11), 2500–2511.CrossRefGoogle Scholar
  9. 9.
    Chien, H. M., Lin, T. H., & Ibrahim, B. (2004). A 4 GHz fractional-N synthesizer for IEEE 802.11 a. In Symposium VLSI Circuits Conference Digest of Technical Papers (pp. 46–49).Google Scholar
  10. 10.
    Lee, J., & Chiu, D. W. (2006). A 7-band 3–8 GHz frequency synthesizer with 1 ns band-switching time in 0.18 μm CMOS technology. In IEEE International Solid-State Circuits Conference Digest of Technical Papers (pp. 126–127).Google Scholar
  11. 11.
    Zheng, H., & Luong, H. C. (2007). A 1.5 V 3.1 GHz–8 GHz CMOS synthesizer for 9-band MB-OFDM UWB transceivers. IEEE Journal of Solid-State Circuit, 42(2), 1250–1260.CrossRefGoogle Scholar
  12. 12.
    Yang, Y.-C., Yu, S.-A., Tang, T., & Lu, S.-S. (2006). A quantization noise suppression technique for ΔΣ fractional-N frequency synthesizers. IEEE Journal of Solid-State Circuit, 41(11), 2500–2511.CrossRefGoogle Scholar
  13. 13.
    Craninckx, J., & Steyaert, M. S. J. (1995). A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler. IEEE Journal of Solid-State Circuits, 30(12), 1474–1482.CrossRefGoogle Scholar
  14. 14.
    Koukab, A., Lei, Y., & Declercq, M. J. (2006). A GSM–GPRS/UMTS FDDTDD/WLAN 802.11a-b-g multi-standard carrier generation system. IEEE Journal of Solid-State Circuits, 40(7), 1513–1521.CrossRefGoogle Scholar
  15. 15.
    Craninckx, J., Liu, M., Hauspie, D., Giannini, V., Kim, T., Lee, J., & Vanbekbergen, P. (2007). A fully reconfigurable software-defined radio transceiver in 0.13 m CMOS. In IEEE International Solid-State Circuits Conference Digest of Technical Papers (pp. 346–347).Google Scholar
  16. 16.
    Nuzzo, P., Vengattaramane, K., Ingels, M., Giannini, V., Steyaert, M., & Craninckx, J. (2009). A 0.1–5 GHz dual-VCO software-defined ΣΔ frequency synthesizer in 45 nm digital CMOS. In Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (pp. 321–324).Google Scholar
  17. 17.
    Huang, D., Li, W., Zhou, J., Li, N., & Chen, J. (2011). A frequency synthesizer with optimally coupled VCO and harmonic-rejection SSB mixer for multi-standard wireless receiver. IEEE Journal Solid-State Circuits, 46(6), 1307–1320.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Wenfeng Lou
    • 1
  • Xiaodong Liu
    • 1
  • Peng Feng
    • 1
  • Nanjian Wu
    • 1
  1. 1.State Key Laboratory for Superlattices and Microstructures, Institute of SemiconductorsChinese Academy of SciencesBeijingPeople’s Republic of China

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