Analog Integrated Circuits and Signal Processing

, Volume 77, Issue 2, pp 299–305 | Cite as

A convex macromodeling of dynamic comparator for analog circuit synthesis

Mixed Signal Letter

Abstract

Equation-based circuit optimization using geometric programming (GP) is a promising analog and mixed-signal design framework that is inherently capable of hierarchical design synthesis. By taking a dynamic comparator as a test vehicle, this paper presents a reduced-complexity cell-level macromodeling method compatible with equation-based circuit optimization using GP. A key contribution of this paper is the demonstration of the complexity-reduction method in creating a convex, empirical, and cell-level macromodel. The variable space reduction is guided by the 1st-order modeling obtained from fundamental understandings on the circuit behavior. The proposed modeling is ideally applicable to create a macromodel exhibiting nonlinear behaviors in time-domain, which are not readily captured in a traditional equation-based modeling approach. The numerical experiment using a dynamic comparator in 0.13 μm CMOS process as a test vehicle indicates that the modeling errors for major performance metrics are less than 5 %, while obtained Pareto-front tradeoff provides useful design guidelines on the architecture-level design exploration.

Keywords

Analog and mixed-signal circuit synthesis Macromodeling Geometric programming Comparator 

References

  1. 1.
    Daems, W., Gielen, G.G.E., & Sansen, W.M.C. (2003a). Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22(5), 517–534CrossRefGoogle Scholar
  2. 2.
    Daems, W. et al. (2003b). Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20(1):1–21Google Scholar
  3. 3.
    Eeckelaert, T., Dames, W., Gielen, G., & Sansen, W. (2004). Generalized simulation-based posynomial model generation for analog integrated circuits. Analog Integrated Circuits and Signal Processing 40(3), 193–203CrossRefGoogle Scholar
  4. 4.
    Eick, M., & Graeb, H. (2012). MARS: Matching-Driven Analog Sizing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31(8), 1145–1158CrossRefGoogle Scholar
  5. 5.
    Kim, J., Vandenberghe, L., & Yang, C.K.K. (2010). Convex Piece-wise Linear Modeling Method for Circuit Optimization via Geometric Programming. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29(11), 1823–1827CrossRefGoogle Scholar
  6. 6.
    Kobayashi, T., Nogami, K., Shirotori, T., & Fujimoto, Y. (1993) A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture. IEEE Journal of Solid-State Circuits 28(4), 523–527CrossRefGoogle Scholar
  7. 7.
    Li, X. (2010). Finding Deterministic Solution From Underdetermined Equation: Large-Scale Performance Variability Modeling of Analog/RF Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29(11):1661–1668CrossRefGoogle Scholar
  8. 8.
    del Mar Hershenson, M., Boyd, S.P., & Lee, T.H. (2001). Optimal Design of a CMOS OpAmp via Geometric Programming. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20(1), 1–21CrossRefGoogle Scholar
  9. 9.
    McConaghy, T., & Gielen, G.G.E. (2009). Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28(8), 1162–1175CrossRefGoogle Scholar
  10. 10.
    Medeiro, F., Perez-Verdu, B., Rodriguez-Vazquez, A., & Huertas, J. (1995). A vertically integrated tool for automated design of Sigma; Delta; modulators. IEEE Journal of Solid-State Circuits 30(7), 762–772CrossRefGoogle Scholar
  11. 11.
    Rutenbar, R.A., Gielen, G.G.E., & Roychowdhury, J. (2007). Hierarchical Modeling, Optimization and Synthesis for System-Level Analog and RF Designs. Proceeding of the IEEE 95(3), 640–669CrossRefGoogle Scholar
  12. 12.
    Tiwary, S.K., Rutenbar, R.A. (2006) Faster, Parametric Trajectory-based Macromodels Via Localized Linear Reductions. In: Proc. of ICCAD, San Jose, CA, pp 876–883Google Scholar
  13. 13.
    Wong, K.L.J., & Yang, C.K.K. (2004). Offset Compensation in Comparators With Minimum Input-Referred Supply Noise. IEEE Journal of Solid-State Circuits 39(5), 837–8404CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Electronics EngineeringKonkuk UniversitySeoulKorea

Personalised recommendations