A low phase noise PLL using Vackar VCO and a wide-locking range tunable divider for V-band signal generation in 65-nm CMOS

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Abstract

This paper presents a low phase noise integer-N phase-locked loop (PLL) for V-band signal generation. To enhance the frequency stability, we use a new class of Vackar voltage-controlled oscillator (VCO) in the PLL. The Vackar VCO achieves a low phase noise performance by effectively suppressing the AM-PM conversion. To properly align the locking range with the output of the VCO, a divider with wide locking range is realized by the current-mode logic (CML) D-flip-flops with tunable load. For spur reduction, an enhanced charge-pump structure is used to reject transient current glitches. With good static and dynamic current matching achieved in the charge pump, the reference spur is suppressed down to −50 dBc. The designed PLL is implemented in a 65 nm RFCMOS process, and the measurement demonstrates a low phase noise signal up to 17 GHz. The in-band phase noise (at 1 MHz offset) and out-band phase noise (at 50 MHz offset) are −103.6 and −126.8 dBc/Hz, respectively. The PLL consumes 50.7 mW and occupies a chip area of 0.9 mm2.

Keywords

Phase-locked loop Voltage-controlled oscillator Current-mode logic CMOS 
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Notes

Acknowledgments

This study was supported in part by the Basic Research Program through the National Research Foundation of Korea (No. 2012-001327) and in part by the ETRI SW-SoC R&BD Center, Human Resource Development Project.

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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Long Thanh Bui
    • 1
  • Tran-Thuyen Chau
    • 1
  • Jong-Wook Lee
    • 1
  1. 1.School of Electronics and InformationKyung Hee UniversitySuwonSouth Korea

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