A 13-bit noise shaping SAR–ADC with dual-polarity digital calibration

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Abstract

We present a new noise shaping method and a dual-polarity calibration technique suited for successive approximation register type analog to digital converters (SAR–ADC). Noise is pushed to higher frequencies with the noise shaping by adding a switched capacitor. The SAR capacitor array mismatch has been compensated by the dual-polarity digital calibration with minimum circuit overhead. A proof-of-concept prototype SAR–ADC using the proposed techniques has been fabricated in a 0.5-μm standard CMOS technology. It achieves 67.7 dB SNDR at 62.5 kHz sampling frequency, while consuming 38.3 μW power with 1.8 V supply.

Keywords

Analog-to-digital converter SAR–ADC Digital calibration Noise shaping 
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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.School of Electrical and Computer EngineeringGeorgia Institute of TechnologyAtlantaUSA

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