Analog Integrated Circuits and Signal Processing

, Volume 74, Issue 2, pp 439–451 | Cite as

Sliding mode audio class-D amplifier for portable devices

  • Gael Pillonnet
  • Remy Cellier
  • Angelo Nagari
  • Philippe Lombard
  • Nacer Abouchi


Audio class-D amplifiers are widely used in industrial and consumer portable electronic devices, such as mobile phones, thanks to their high efficiency. However, these amplifiers have a limited linearity due to their switching behavior and also a limited control bandwidth. To overcome these major drawbacks, this paper introduces a self-oscillating control technique based on the sliding mode theory which combines a large control bandwidth and a spread spectrum technique. A high power supply rejection, which is a crucial parameter in modules directly connected to a noisy battery, has also been achieved by introducing a variable hysteresis window. Theoretical analysis, behavioral and electrical simulations are discussed in detail in this paper. An integrated circuit using 0.13 μm CMOS process has been realized focused on mobile phone applications (0.8 W, 3.6 V and 8 Ω). The audio amplifier achieves 97 dB(A) signal-to-noise ratio, 0.02 % harmonic distortion and up to 80 dB of power supply rejection. The die area is smaller than 0.4 mm2 while keeping more than 90 % efficiency at 1 W.


Switching audio amplifier Class D Self-oscillating Sliding mode control 

1 Introduction

Linear amplifiers, such as class AB, have limited efficiency because their power transistors operate in linear region. In order to improve the efficiency, the switching amplifiers, also called class D, are widely used as their power transistors operate in the triode and cut-off regions thus reducing power dissipation [1, 2]. Consequently, they become an attractive solution for battery-powered applications used in hearing aids, headphones, mobile phones, smartphones and notebook computers where power efficiency is a key factor in extending the life of the battery.

Unfortunately, the switching power stage of the class D introduces nonlinearities and noise into the audio output signal. Sources of nonlinearity include the finite rise and fall switching time, dead time during switching and other parameters studied in [1, 3, 4]. The power supply can be an additional source of noise and nonlinearity due to the supply common access resistance of numerous noisy circuits. Standard ternary Pulse Width Modulation (PWM) open-loop class D provides low power supply rejection ratio (PSRR), especially with a full-scale audio signal. Existing open-loop structures have relied on a highly accurate power stage and clean power supply for achieving good performance (PSRR and linearity) [1].

Feedback topologies have been introduced around the class D switching power stage to improve the power supply immunity and to correct the errors introduced by the switching. In addition to the standard PWM feedback [5, 6] shown in Fig. 1, several strategies have been proposed to improve the ratio between the control bandwidth and additional consumption introduced by the controller. Some of those solutions are: control based on sigma delta modulator [7], controlled oscillated modulator [8, 9, 10], digital feedback [11, 12], and hysteresis control (HC) [13, 14, 15]. However, most of them provide a limited bandwidth to correct all the power stage non-linearity and/or to limit the effect of a noisy power supply. The objective of this work is to improve the hysteresis control solution, which showed the best performance in previous work [13, 14, 15], and to improve the audio performance, especially linearity and power supply immunity.
Fig. 1

Basic closed-loop PWM class D amplifier

This paper presents an integrated class D amplifier based on HC, called here sliding mode, using a variable hysteresis window to allow a higher PSRR. The application target of this research is to provide a suitable solution for “hands-free” loudspeaker into the mobile phones, having as classical requirement to deliver 1 W in an 8 Ω load. The authors in this paper will extend their previous work [16, 17, 18]. Some preliminary results are already published in [16] and are compared with the existing Pulse Width Modulation control solution in [17]. These papers give a brief overview of the topology for confidential reasons. As the related patent [18] has been published, the authors can explain the design in more detail. This article gives additional theoretical aspects and explains some practical considerations. The following section explains the limitation of the classical method of HC due to constant hysteresis windows. Moreover, the modulation, power supply immunity performance and the effect of control op-amp bandwidth are explained in detail. Finally, correlated with experimental results, additional information about the efficiency versus output power and a state-of-the-art comparison are provided in the last section.

2 Limitations of classical hysteresis feedback

2.1 Principle of hysteresis control

The block diagram of a hysteresis feedback class D amplifier is illustrated in Fig. 2. The control loop (based on an active first order integrator) integrates the switched output voltage V out and reference audio signal V in. The hysteresis block compares the integrated error signal with respect to its window width in order to generate a high frequency pulse train signal V c which drives the inverting power stage. The feedback signal is the output signal taken from the power stage output, before the passive low pass filter, to reduce the number of pins.
Fig. 2

Basic hysteresis control scheme

The operating principle of this topology is to limit the amplitude of the integrated error signal, S, by a hysteresis cycle. The integrated error signal, also called the sliding surface, is given by:
$$ S = - \frac{1}{\tau }\int\limits_{0}^{t} {\left( {V_{\text{in}} - V_{\text{out}} } \right)} dt $$

If the signal error frequency spectrum is outside the audio bandwidth, the error on the output (derived from S) is inaudible because it falls from the audible frequency range. In this case, this control strategy can be put to practical use even in the high-end audio application.

One important characteristic of HC is the ability to reject all errors introduced in the direct path consisting of an active integrator, a hysteresis window and the power stage. This control has almost one-cycle response by forcing the error between the averaged switching variable V out and the control reference V in in the hysteresis window width at each cycle.

Figure 3 shows the sliding surface S and the output signals V out and V ls (time and voltages are normalized). These results are obtained from a behavioral model using Matlab/Simulink where all components are considered as ideal. It can be seen that the switching frequency is variable, dependent on the modulation index, and the signal error varies with the same frequency. The modulation index M is the ratio between input voltage V in and power supply voltage V pow.
Fig. 3

Transient simulation: sliding surface S and output waveforms

2.2 Power stage topology: H-bridge in binary modulation

In battery-powered applications, the most widely-used class D topology is a differential implementation of the power stage. This H-bridge has two half-bridge switching power stages, composed of two complementary switches providing an opposite polarity pulse train to the load (Fig. 4). Each half-bridge contains two opposite MOS transistors connected to a single supply V pow (typically around 3.6 V if connected to classical Li-ion battery) and the ground. The differential nature of the power stage means that it can deliver twice the output signal and four times the output power compared to the single-ended implementations.
Fig. 4

H-bridge power stage

With conventional differential operation, also called binary modulation, the output polarity of the “Plus stage” is opposite to that of the “Minus stage”, because there are only two operating states on the Plus and Minus stage outputs: {high;low} or {low;high}. However, conventional class D amplifiers use three-state modulation, also called ternary modulation. The benefits of this are to reduce the output differential-mode (but increase the common-mode) and to increase the efficiency at low power by reducing the ripple output current [1]. In our proposed approach, the binary modulation is used as in [14], because the synchronization of the three-state modulation schemes is a challenge in order to avoid cross modulation in the H-bridge configuration. In Sect. 5, the effects of the binary modulation on the efficiency at low power are characterized.

2.3 Advantages

The main advantage of HC compared to other class D feedback topologies is its control bandwidth. The loop bandwidth is similar to the switching frequency because the system has about one-cycle response [19]. Moreover, the error rejection, also called noise transfer function (NTF), has the same shape as a second-order loop function. Figure 5 shows the NTF of HC with an idle switching frequency of 500 kHz and compare to high-pass second-order function with 500 kHz natural frequency (no damping). For example, a perturbation at the frequency of 20 kHz added to the output is almost reduced by 60 dB, making this architecture very robust to additional perturbations.
Fig. 5

NTF of class D hysteresis control

The second benefit is its simple implementation: HC does not have any carrier generators in the design compared to PWM control [20] and needs only a first-order active integrator due to its intrinsic second-order NTF. This is an advantage as the design complexity allows low idle consumption and low area (less capacitance value).

The first-order hysteresis naturally oscillates between the sliding surface, by consequence there is no instable condition as in classical PWM class D design. Moreover, the system is also very robust against the output filter variation since it is not included in the loop; thus the external and on-chip circuitry variations have no impact on the stability.

This proposed approach has the additional advantage of widening the switching frequency range then reducing electro-magnetic interference (EMI) due to the variable switching frequency. On the other hand, this variation may decrease the audio quality, as explained below.

2.4 First limitation: switching frequency variation

The instantaneous switching frequency depends on external parameters (power supply, input level) and on-chip parameters (process variation). In the H-bridge configuration with a constant hysteresis window, the switching frequency can be expressed as follows:
$$ f_{\text{sw}} = V_{\text{pow}} \frac{{1 - M^{2} }}{2\Updelta \tau } $$
The switching frequency is directly related to the supply voltage V pow, the modulation index M, the integrator time constant τ and the hysteresis window width, Δ. As shown in Fig. 6, the switching frequency changes with the input signal level [16]. This result is validated with a behavioral model using ideal elements.
Fig. 6

Instantaneous switching frequency during one input signal period

The spread of the switching frequency has to be carefully designed to ensure that the lowest frequency is higher than the audio bandwidth; if this condition is not achieved, the audio quality decreases dramatically generating folding noise into the audio band. Moreover, the integration of multi-channels (stereo application) combined with unsynchronized frequencies could generate crosstalk. Such effects can be greatly reduced acting as follow: (i) the modulation index could be limited (but reducing the maximal output power and the output voltage dynamic), (ii) the power supply variation could be managed (but introducing a costly power management unit), (iii) the switching frequency at each channel could be separated and (iv) the layout and substrate isolation would have to be carefully designed (but increasing the silicon area). Therefore, to circumvent the large switching frequency range, the introduction of variable hysteresis windows is suggested to reduce the dependency of the switching frequency on the power supply (see Sect. 3).

On the other hand, the spread spectrum is an attractive property for electromagnetic-compliant (EMC) designs at a high modulation index where the conducted and radiated emissions could be a problem for high density PCB e.g. in a mobile phone application.

2.5 Second limitation: low power supply immunity

The PSRR is one of the primary characteristics for a high end class D amplifier integrated in a cell phone. In fact, its power supply is connected directly to the battery and contains system-dependent noise patterns such as the GSM burst at 217 Hz. System and audio specifications require such noise to be rejected. An efficient feedback around the switching power stage can significantly reduce the regulation requirement of the supply source. The benefit of the high control bandwidth in hysteresis topology provides an advantage compared to other feedback topologies. However, the PSRR is not directly linked to the NTF because this is calculated from additional perturbations on the output. Thus, the PSRR is the ability of the system to reject power supply variation, added and/or multiplied at different class D stages (integrator, hysteresis bloc and power stage). For this reason, the following simulations keep the NTF and PSRR separate.

The intrinsic PSRR from the modulation and from the control must also be dissociated. In the open-loop structure (without feedback), there is intrinsic PSRR due to the H-bridge configuration in binary and ternary modulations [12]. The load differential connection reduces the dependency from the power line because the noise is applied on the two half bridges with the same polarity. In theory, the PSRR depends on the input level (i.e. PSRR is infinite at zero input voltage). However, the intrinsic PSRR cannot reach the audio specifications over a large input signal voltage range. Efficient feedback control architecture while taking into account the electrical implementation is needed to improve the PSRR.

In the following, the term PSRR is taken as the intrinsic PSRR of the feedback (called PSRRcontrol) to show the additional benefit of the control. The PSRRtotal is defined in (3) as the addition of the control’s PSRR and the modulation’s PSRR due to the binary modulation, such that:
$$ {\text{PSRR}}_{\text{total}} = {\text{PSRR}}_{\text{control}} + {\text{PSRR}}_{\text{modulation}} $$
To implement the HC, prior work integrated a constant hysteresis window [13, 14, 15]. In this case, the hysteresis controller could be realized based on the usual Schmitt trigger, shown in the Fig. 7.
Fig. 7

Hysteresis window with Schmitt trigger

However, this structure is limited if we want to obtain a high PSRR. For the effect of fixed hysteresis windows on the supply noise immunity, the main problem comes from the variation of the hysteresis width as a function of the supply voltage. At high frequency, the sliding mode surface S varies between the lower and upper windows and it also follows the frequency of the power supply variation (Fig. 8). S can be simplified in both terms, thus giving:
$$ S = \Updelta S_{\text{cm}} + \Updelta S $$
where ΔS represents the high frequency variation due to hysteresis modulation and ΔS cm, the variation due to the hysteresis common mode (U+ + U)/2 variation as a function of the power supply.
Fig. 8

Sliding surface and output voltage when the power supply varies

The common mode of hysteresis can be calculated using the following:
$$ \Updelta S_{\text{cm}} = \frac{{U^{{_{ + } }} + U^{{_{ - } }} }}{2} = \left( {1 - \alpha } \right)\frac{{V_{\text{ref}} }}{2} + \alpha V_{\text{pow}} $$
where \( \alpha = \frac{{R_{1} }}{{R_{1} + R_{2} }} \)
The output voltage variation can easily be derived in the audio band, such that:
$$ V_{\text{out}} = V_{\text{in}} - \tau \frac{{d\Updelta S_{\text{cm}} }}{dt} $$
If the power supply is considered as a pure sinusoidal signal V pow = Asin(2πf pow t) and from the last equation, the output voltage is equal to:
$$ V_{\text{out}} = V_{\text{in}} - 2\pi \tau \alpha f_{\text{pow}} A\cos \left( {2\pi f_{\text{pow}} t} \right) $$
Thereby, the output voltage is composed of the input signal and a residual power supply component due to the variation of the hysteresis common mode. By definition [1], the PSRR can be expressed as:
$$ {\text{PSRR}} = 2\pi \tau \alpha f_{\text{pow}} $$

Simulated PSRR using the behavioral model and calculated PSRR from Eq. (8) are compared for an idle switching frequency of 500 kHz, α equal to 0.1 and a modulation index of 0.7 (corresponding to a high amplitude output level). Despite the ability of the HC to reject the errors shown by NTF in Fig. 5, the implementation of the hysteresis windows by using the Schmitt trigger limits the power rejection: only 40 dB at the GSM burst frequency i.e. 217 Hz. To avoid this problem, we suggest another implementation of the hysteresis window, presented in the next section.

3 Hysteresis feedback with variable hysteresis window

We suggest an architecture based on a variable hysteresis window to reduce the dependency of the switching frequency on the power supply and to improve the power supply immunity; both limitations of existing HC solutions have been described above.

3.1 Principle

The two limitations of the Schmitt trigger come from (i) the constant differential mode voltage and (ii) the common mode voltage variation as a function of the power supply. The proposed solution is based on a constant common mode and a variable differential mode of the hysteresis windows. The boundaries of the windows are chosen to obtain the following conditions:
$$ U^{ + } = V_{\text{refcm}} + \alpha V_{\text{pow}} \;\& \;U^{ - } = V_{\text{refcm}} - \alpha V_{\text{pow}} $$
where, V refcm is the fixed reference voltage.
The width of the hysteresis window U dm depends on the power supply and is centered on a constant voltage V refcm independent of the power supply variation:
$$ U_{\text{dm}} = \Updelta = U^{ + } - U^{ - } = 2\alpha V_{\text{pow}} \;\& \;U_{\text{cm}} = \frac{{U^{ + } + U^{ - } }}{2} = V_{\text{refcm}} $$
Figure 9 clearly shows the well-known schematic of a hysteresis window, chosen for our implementation.
Fig. 9

Implementation of the variable hysteresis window

3.2 First improvement: reducing the variation of the switching frequency

The variable hysteresis window width limits the switching frequency variation due to the power supply voltage range. In the proposed architecture, the switching frequency f sw can be expressed using Eqs. (2) and (10):
$$ f_{\text{sw}} = \frac{{1 - M^{2} }}{4\alpha \tau } $$

By comparing Eqs. (2) and (11), we observe that the switching frequency variation therefore decreases regardless of the supply voltage. Due to the reduced switching frequency variation, the error rejection capability is maintained because it is directly linked to the switching frequency. Thus, the performance of the feedback is not reduced as a function of the power supply and the design manages more easily with a large power supply range, as in cell phone applications.

3.3 Second improvement: increase the power supply immunity

The fixed hysteresis common mode, U cm, suppresses the frequency variation due to the power supply noise on the sliding surface. With the proposed hysteresis, S can be expressed as:
$$ S = \Updelta S_{\text{cm}} + \Updelta S\;{\text{with}}\;\Updelta S_{\text{cm}} = U_{\text{cm}} = \frac{{U^{ + } + U^{ - } }}{2} = V_{\text{refcm}} $$
Thus, the output voltage variation can easily be derived in the audio band, as
$$ V_{\text{out}} = V_{\text{in}} - \tau \frac{{d\Updelta S_{\text{cm}} }}{dt} = V_{\text{in}} $$
In theory, the PSRRcontrol is now not limited by the effect of the hysteresis windows, making this solution very robust to perturbations, such as 217 Hz burst noise in the GSM cell phone. Figure 10 compares the PSRRcontrol of constant common mode hysteresis (proposed approach) with that of the variable common mode. The PSRR is half that of the NTF (+6 dB) because the power-supply variation is introduced twice by the two half-bridge power supplies.
Fig. 10

PSRR improvement with hysteresis with constant common mode

4 Circuit implementation

In this section, the effects of electrical implementation of the controller are discussed: (i) the finite bandwidths of an operational amplifier (op-amp) integrator, (ii) the delays introduced by the comparators and the power stage, and (iii) the hysteresis boundary generation. This non-ideal behavior reduces the performance of the HC. The practical implementation in double oxide 0.13 μm CMOS process is also described in this section.

4.1 Binary variable sliding mode class D amplifier topology

The complete schematic of our proposed fully-integrated solution, called the Binary Variable Sliding Mode Audio class D Amplifier, is given in Fig. 11. It is a single input differential output class D, composed of a controller (active integrator), a comparator with a variable hysteresis window, the driver and an H-bridge power stage. A differential input could also be obtained easily without introducing a differential op-amp. A CMOS 0.13 μm process with a double oxide option was used to make the integrated circuit compatible with the 5 V power supply voltage. The output low pass filter is composed of external inductive and capacitive components (typical cut-off frequency 30 kHz). This filter could be removed if the speaker is sufficiently inductive, but it increases the static current consumption (see Sect. 5).
Fig. 11

Electrical schematic of the proposed solution

4.2 Effect of the non-ideal active integrator

The switching frequency expressed in Eq. (11) does not include the effects of the electrical implementation. The switching frequency depends on the dominant pole τa and the finite DC gain A of the op-amp of the integrator function. This pole has to be taken into account in the design to predict the switching frequency. An analytical expression is given below to determine the hysteresis window width needed to compensate for the reduction of the switching frequency due to the op-amp gain bandwidth. The transfer function of the integrator with a non-ideal op-amp can be expressed as:
$$ C(s) = \frac{A}{{1 + \left[ {\left( {1 + A} \right)\tau + \tau_{a} } \right]s + \tau_{a} \tau s^{2} }} \approx \frac{A}{{1 + \tau_{i} s}} $$
where, τi = (1 + A) τ+τa and we suppose that τaτ is not a dominant pole.
The differential output voltage V out (when no input signal is applied) is a square wave with an amplitude of 2V pow centered at zero. It can be calculated in the s-domain and in steady-state so that:
$$ V_{\text{out}} (s) = 2V_{\text{pow}} \sum\limits_{k = 0}^{N} {\left( { - 1} \right)^{k} \frac{{e^{{ - k\frac{{t_{\text{ws}} }}{2}s}} }}{s}} - \frac{{V_{\text{pow}} }}{2s} $$
The signal V i can be expressed for the same previous conditions, so that:
$$ V_{i} (s) = \frac{A}{{1 + \tau_{i} s}}\left( {2V_{\text{pow}} \sum\limits_{k = 0}^{N} {\left( { - 1} \right)^{k} \frac{{e^{{ - k\frac{{t_{\text{sw}} }}{2}s}} }}{s}} - \frac{{V_{\text{pow}} }}{2s}} \right) $$
and in the time domain:
$$ V_{i} (t) = AV_{\text{pow}} \sum\limits_{k = 0}^{N} {\left( { - 1} \right)^{k} \left( {1 - e^{{\frac{{\left( {k - N} \right)t_{\text{sw}} }}{{2\tau_{i} }}}} } \right)} - \frac{{AV_{\text{pow}} }}{2}\left( {1 - e^{{ - \frac{{Nt_{\text{sw}} }}{{2\tau_{i} }}}} } \right) $$
By definition, if N is even, then V i(N) = −αV pow, and we obtain:
$$ \alpha = \mathop {\lim }\limits_{p \to + \infty ,N = 2p + 1} A\sum\limits_{k = 0}^{N} {\left( { - 1} \right)^{k} \left( {1 - e^{{\frac{{\left( {k - N} \right)t_{\text{sw}} }}{{2\tau_{i} }}}} } \right)} - \frac{A}{2}\left( {1 - e^{{ - \frac{{Nt_{\text{sw}} }}{{2\tau_{i} }}}} } \right) $$
Thereby, Eq. (10) gives the hysteresis window width Δ in order to have the desired switching frequency 1/t s with a non-ideal op-amp having a static gain, A, and a dominant pole, τa. Figure 12 shows the ratio between the hysteresis width using a real op-amp and one using an ideal one as a function of the op-amp Gain BandWidth (GBW) in Hertz. The modified delta is the ratio between the delta obtained by Eq. (18) and the one from Eq. (10). When the op-amp becomes ideal (at high bandwidth), the normalized delta tends to zero. If an op-amp with a 1 MHz GBW product is used the hysteresis width could be approximately halved compared to that given in (10). This reveals a non-negligible effect on the op-amp GBW.
Fig. 12

Hysteresis width compensation in function to the op amp GBW (in Hertz)

With Eq. (18), the designer can predict the reduction in the switching frequency. The desired frequency can be compensated for by reducing the hysteresis width. In other words, the active integrator does not need a high bandwidth op-amp because of this predictability. Thus, the static consumption of the integrator could be reduced.

4.3 Delay induced switching frequency variation

The switching frequency also depends on the total delay in the direct path, t d, due to the commutation times of comparators, drivers and power stages. It can be expressed as:
$$ f_{\text{sw}} = \frac{{1 - M^{2} }}{{4\left( {\alpha \tau + \left( {1 - M^{2} } \right)t_{\text{d}} } \right)}} $$
The variation of f sw with modulation index for different delays is shown in Fig. 13 obtained from Eq. (19). The delay can be used to reduce the switching frequency dependence on the input voltage. On the other hand, the NTF is reduced to a first-order shape instead of second-order [19] if the delay increases. In fact, the NTF of the HC with delay cannot exceed the NTF obtained by a self-oscillating topology [9, 10] based on the same delay. Figure 14 shows the NTF including 10 ns delay at a 500 kHz idle switching frequency. With a 10 ns delay, the NTF of our sliding mode control is equal to the NTF of a delay-based self-oscillating architecture [9].
Fig. 13

Switching frequency variation with the delay

Fig. 14

NTF with 10 ns delay

4.4 Generation of the hysteresis boundaries

Figure 15 shows the schematic of the window generation block used to generate the hysteresis boundary voltages U+ and U−.
Fig. 15

The proposed voltage boundary generation for the hysteresis window

The electrical equations of the hysteresis window are given by the following relations:
$$ \left\{ {\begin{array}{*{20}c} {U^{ - } = - \frac{{R_{1} }}{{R_{0} }}V_{\text{pow}} + V_{\text{ref}} \frac{{R_{3} }}{{R_{2} + R_{3} }}\left( {1 + \frac{{R_{1} }}{{R_{0} }}} \right) = V_{\text{refcm}} - \alpha V_{\text{pow}} } \\ {U^{ + } = \frac{{R_{5} R_{1} }}{{R_{4} R_{0} }}V_{\text{pow}} + V_{\text{ref}} \left( {1 + \frac{{R_{5} }}{{R_{4} }} - \frac{{R_{5} R_{3} }}{{R_{4} \left( {R_{2} + R_{3} } \right)}}\left( {1 + \frac{{R_{1} }}{{R_{0} }}} \right)} \right) = V_{\text{refcm}} + \alpha V_{\text{pow}} } \\ \end{array} } \right. $$

A flip-flop combines both comparator outputs as they behave like one comparator with hysteresis, as shown in Fig. 9. The commutation times of comparators were carefully designed to have a small delay i.e. a few ns in the direct path and thus guarantee a high PSRR. The calculated hysteresis width is around 200 mV which does not produce too high an amplitude on the integrator output V c.

4.5 Integrator

As the average switching frequency is approximately 300 kHz in normal test mode, the integrator time constant τ, defined by the RC product, can be programmed in order to test control performance with different switching frequencies. The quiescent current used by the active integrator is 500 μA for a typical GBW = 10 MHz.

4.6 Switched power stage

The power stage has been designed to optimize efficiency under an 8 Ω load at 1 W of maximum output power. The ON resistances of sized MOS transistors are approximately equal to 100 mΩ and the parasitic gate capacitances are estimated at 100 pF. The switching losses, associated with charging and discharging the gate capacitance of power devices every cycle, are low enough to provide relative high efficiency at low output power. The power stage was designed to be robust for large switching current variation by controlling the fall and rise time of the gate drivers. The dead-time also adapts to the speed of transistor turn-off, typically a few nanoseconds.

The die micrograph in Fig. 16 shows the layout of the amplifier with the H-bridge output stage. The core area is 0.4 mm2, and the power stage is 80 % of the total area of the integrated class D amplifier.
Fig. 16

Layout of the proposed solution

5 Experimental results

All experimental measurements were made using Audio Precision equipment (AP2700 series). All results were taken with V pow = 3.6 V (nominal battery voltage), external low pass filter with a cutoff frequency equal to 30 kHz (L = 50 μH), and an output resistance R = 8 Ω. In the following measurements, the idle switching frequency is 470 kHz (at zero input signal).

5.1 Idle consumption and power efficiency

The static current is equal to 0.7 mA per channel without load, including the power stage (200 μA) and control (500 μA). Due to binary modulation, the static current rises up to 4.6 mA per channel when the load is connected (L = 150 μH, R = 8 Ω). Figure 17 presents the binary modulation at zero input level. The Plus and Minus power stages have opposite phases thus creating idle current in the load. In this configuration, the ripple output current (Fig. 17, I load = 33 mArms at idle) due to the binary modulation is dissipated into the load (however, without creating audible sound). The switching frequency could be increased reducing ripple output current. At 1.1 MHz, the static current is 3.9 mA. However, the static current rises to 11.5 mA with real micro-speakers because the equivalent inductance is lower (i.e. L = 50 μH, R = 8.2 Ω, f sw = 1.1 MHz). This idle current could be reduced by introducing a synchronized ternary modulation.
Fig. 17

Plus and minus output voltages and load current without input signal

In the proposed circuit, the duty cycle error is corrected as a consequence of the high dc gain due to the sliding mode control. The measured output offset in this case is 3.1 mV due to the offset of the integrator op-amp mainly due to the mismatch in the differential pair. Finally, at full output power, the measured efficiency is 90 % as shown in Fig. 18. All the above characteristics are key factors in increasing battery life time in cell phones.
Fig. 18

Efficiency of the proposed solution

5.2 Static and dynamic noise

The noise level without input signal is equal to 45 μVrms, generating no audible noise with standard micro-speakers (sensitivity less than 70 dBspl/10 cm/W). The measured residual noise is 30 μV A-weighted over the whole audio bandwidth [100 Hz, 22 kHz]. The noise level is unaffected by increasing the switching frequency.

The Total Harmonic Distortion plus Noise (THD + N) has been measured over a 20 Hz–22 kHz bandwidth. Figure 19 shows the THD + N as a function of the output voltage level. The class D exhibits −82 dB of THD (0.0075 %) at 125 mW (1 Vrms with 8 Ω, left channel) with 1 kHz input frequency. At 6 kHz, the THD is lower than 0.043 % in the same conditions. The THD + N performance is similar at 1 MHz idle switching frequency: the error introduced by the switching is larger but the control bandwidth is higher. As shown in Fig. 14, the low frequency gain is limited by the delay in the direct path.
Fig. 19

THD + N versus output level (in Volt) at 1 kHz

In stereo mode (Fig. 20), the THD reaches 0.023 % (72 dB) when the same input signals and switching frequencies are fixed in the two channels (worst case conditions). This result proves that a self-oscillating solution could be an alternative solution to fixed switching frequency even in a multichannel configuration.
Fig. 20

Output spectrum at 1 Vrms in mono (blue) and stereo mode (red) (Color figure online)

5.3 Power supply rejection

In the PSRR test, the input is a 1 kHz pure sine wave at full scale. To quantify the ripple rejection capability, the PSRR test is performed by inducing an intentional ripple in the power supply. A 600 mVpp square wave signal at 217 Hz is applied. These conditions represent power supply variation during GSM RF emission. The main benefit of the sliding mode is the high PSRR (here, 70 dB) due to a loop bandwidth equal to the switching frequency even if binary modulation is used. The Fig. 21 shows the output spectrum when a 217 Hz square wave at 100 mV is applied on the 3.6 Vdc power supply. The circuit can be operated directly connected to a noisy power supply such as a cell phone battery.
Fig. 21

FFT for 1 W output power and 1 kHz input signal with square wave on power supply

5.4 Switching frequency variation

As predicted in Eq. (11), the switching frequency varies with the modulation index. This has been tested for a sinusoidal input reference (1 Vrms at 1 kHz, Figs. 21, 22). The results match well with theoretical predictions and simulation results. Spectral analysis of output HF components shows the advantage of spread spectrum EMI compared to PWM modulation, due to the varying switching frequency. The measurements are in line with the previous simulations. In addition, the modulation components do not change at low modulation index (no spread spectrum appears), but the power delivered to the load is very low in this case.
Fig. 22

Switching frequency variation versus modulation index

5.5 Class-D audio amplifier comparison

Table 1 compares previous class D amplifiers with those in our work, including the HO- and SO-based feedback (Hysteresis Oscillation and Self-Oscillation, respectively). The PSRR is not included due to the lack of a clearly comparable experimental condition. However, the THD results give the loop capability to reduce the unwanted adding perturbation in the direct path. Overall, the amplifier combines good audio performance with low dissipation. This design can therefore clearly compete with any of the switching audio amplifier ICs on the market.
Table 1

Comparison of class D amplifiers in mobile applications


CMOS process (nm)

Loop topology

Static current @ 8 Ω (mA)

Area (mm²)

THD @1 kHz–500 mW (%)


This work


















0.05 ***




































* With load, ** P MAX is defined @1 % THD, *** P OUT = 60 mW

6 Conclusion

In this paper, a switching audio amplifier based on sliding mode control is proposed and its performance measured. The advantages of this structure compared with conventional architectures are its low design complexity allowing lower idle consumption. The power supply rejection and switching frequency variation have also been improved by introducing a variable hysteresis window. The experimental integrated circuit has a PSRR (70 dB), linearity (<0.02 %) and SNR (97 dB) similar to present solutions. Therefore, the proposed circuit is suitable for embedded applications such as audio amplifiers in cell phones even in stereo mode. Future research will be to implement this technique in synchronized ternary modulation to decrease the idle current and reduce the crosstalk.


  1. 1.
    Nielsen, K. (1998). Linearity and efficiency performance of switching audio power amplifier output stages: A fundamental analysis. In 105th AES convention. Paper number 4838. Copenhagen: AES.Google Scholar
  2. 2.
    Nagari, A. (2011). Tutorial review: audio amplifiers in mobile platforms. In Proceedings of Analog Integrated Circuits and Signal Processing. Croatia: IEEE.Google Scholar
  3. 3.
    Pietro, A., Flemming, N., & Lars, R. (2005). Time domain analysis of open loop distortion in class D amplifier output stages. In 27th International AES conference (pp. 3–4). Hillerød: AES.Google Scholar
  4. 4.
    Lau, W. H., & Chung, S. H. (1999). Analytical technique for calculating the output harmonics of an H-bridge inverter with dead time. IEEE Transactions on Fundamental Theory and Applications, 46(5), 617–627.CrossRefGoogle Scholar
  5. 5.
    Kao, C. H., Tsai, P. Y., Lin, W. P., & Chuang, Y. J. (2008). A switching power amplifier with feedback for improving total harmonic distortion. Proceedings of Analog Integrated Circuits and Signal Processing, 55(3), 205–212.CrossRefGoogle Scholar
  6. 6.
    Guilherme, D., Guilherme, J., & Horta, N. (2011). Automatic topology selection and sizing of class-D loop-filters for minimizing distortion based on an evolutionary optimization kernel. Proceedings of Analog Integrated Circuits and Signal Processing, 66(1) 49–59.Google Scholar
  7. 7.
    Gaalaas, E., Liu, B. Y., Nishimura, N., & Adams, R. (2005). Integrated stereo ΔΣ class D amplifier. IEEE Journal of Solid-State Circuits, 40(12), 2388–2397.CrossRefGoogle Scholar
  8. 8.
    Lee, J., Copani, T., Mayhugh, T. Jr., Aravind, B., Kiaei, S. & Bakkaloglu, B. (2011). A 280 mW, 0.07% THD + N class-D audio amplifier using a frequency-domain quantizer. Proceedings of Analog Integrated Circuits and Signal Processing, 72(1) 173–186.Google Scholar
  9. 9.
    Huffenus, A., Pillonnet, G., Abouchi, N., Goutti, F., Rabary, V. & Specq, C. (2010). A phase-shift self-oscillating stereo class-D amplifier for battery-powered applications. In IEEE International Symposium of Circuits and Systems (pp. 769–772). Paris: ISCAS.Google Scholar
  10. 10.
    Soo-Hyoung, L., Jae-Young, S., & Ho-Young, L. (2004). A 2 W 92% efficiency and 0.01% THD + N class-D audio power amplifier for mobile applications, based on the novel SCOM architecture. Proceedings of the IEEE Custom Integrated Circuits Conference, 46, 291–294.Google Scholar
  11. 11.
    Midya, P., Roeckner, B., & Paulo, T. (2006). High performance digital feedback for PWM digital audio amplifiers. In 121th AES convention, paper number 6862. Ilmenau: AES.Google Scholar
  12. 12.
    Biallais, A., de Buys, F., de Saint-Moulin, R., Dooper, L., Putzeys, B., Reefman, D., Rutten, R., Tol, J., & van den Boom, J. (2006). A digital class D amplifier with power supply correction. In 121th AES convention, paper number 6860. San Francisco: AES.Google Scholar
  13. 13.
    Ge, T., Tan, M. T., & Chang, J. S. (2005). Design and analysis of a micropower low-voltage bang–bang control class D amplifier. IEEE International Symposium on Circuits and Systems, 1, 224–227.Google Scholar
  14. 14.
    Rojas-Gonzalez, M. A., & Sanchez-Sinencio, E. (2007). Design of class D audio amplifier IC using sliding mode control and negative feedback. IEEE Transaction on Consumer Electronics, 53(2), 209–217.Google Scholar
  15. 15.
    Rojas-Gonzalez, M. A., & Sanchez-Sinencio, E. (2009). Low power high efficiency class D audio amplifiers. IEEE Journal of Solid-State Circuit, 44(12), 3272–3284.CrossRefGoogle Scholar
  16. 16.
    Pillonnet, G., Cellier, R., Abouchi, N. & Nagari, A. (2008). An integrated class D amplifier based on sliding mode control. In IEEE Integrated Circuit Design and Technology and Tutorial ICICDT (pp. 117–120). Austin: IEEE.Google Scholar
  17. 17.
    Pillonnet, G., Cellier, R., Abouchi, N., & Nagari, A. (2008). A topological comparison of PWM and hysteresis control in switching audio amplifiers. In IEEE Asia Pacific Conference on Circuits and Systems APCCAS (pp. 668–671). Macao : IEEE.Google Scholar
  18. 18.
    Pillonnet, G., & Cellier, R. (2011). Switching amplifier. US Patent Number 7,961,047.Google Scholar
  19. 19.
    Berkhout, M. (2009). Audio class D amplifiers in mobile application. In IEEE International Symposium on Circuit and Systems (pp. 1169–1172). Taipei: ISCAS.Google Scholar
  20. 20.
    Choi, Y., Tak, W., Yoon, Y., Roh, J., Kwon, S., & Koh, J. (2012). A 0.018% THD + N, 88-dB PSRR PWM class-D amplifier for direct battery hookup. IEEE Journal of Solid-State Circuits, 47(2), 454–463.CrossRefGoogle Scholar
  21. 21.
    Torres, J., Colli-Menchi, A., Rojas-González, M. A., & Sánchez-Sinencio, E. (2011). A low-power high-PSRR clock-free current-controlled class-D audio amplifier. IEEE Journal of Solid State Circuits, 46(7), 1553–1561.CrossRefGoogle Scholar
  22. 22.
    Samala, S., Mishra, V., & Chakravarthi, K. C. (2010). 45 nm CMOS 8 Ω class D audio driver with 79% efficiency and 100 dB SNR. In IEEE International Symposium on Solid-State Circuits Digest of Technicla Papers (pp. 86–87). Paris: IEEE.Google Scholar
  23. 23.
    Teplechuk, M., Gribben, T., & Amadi, C. (2011). Filterless integrated class-D audio amplifier achieving 0.0012% THD + N and 96 dB PSRR when supplying 1.2 W. In IEEE International Symposium on Solid-State Circuits Digest of Technical Papers (pp. 240–242). Santa Monica: IEEE.Google Scholar

Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  • Gael Pillonnet
    • 1
  • Remy Cellier
    • 1
  • Angelo Nagari
    • 2
  • Philippe Lombard
    • 1
  • Nacer Abouchi
    • 1
  1. 1.CPE Department, Institute of Nanotechnology, University of LyonVilleurbanneFrance
  2. 2.ST Ericsson, Advanced IP DivisionGrenobleFrance

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