Analog Integrated Circuits and Signal Processing

, Volume 73, Issue 3, pp 801–808 | Cite as

Time-based all-digital sigma–delta modulators for nanometer low voltage CMOS data converters

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Abstract

A phase-based delta–sigma (ΔΣ) analog-to-digital converter (ADC) is proposed and the idea is demonstrated using two architectures. The first architecture adopts a delay-locked-loop (DLL) mechanism. It is realized by a modification of a DLL using a voltage-controlled delay line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed ΔΣ ADC achieved 50.5 dB SNDR or 8.09 bits resolution for a 10 MHz signal bandwidth. The second architecture adopts a combination of voltage-controlled and digitally-controlled delay lines (VCDL–DCDL) as the phase-domain counterparts of an ADC–DAC in a traditional delta–sigma modulator. Simulation results of the new modulator achieve a 57.8 dB SNR, or a 9.28 bit over a 10 MHz bandwidth.

Keywords

Analog to digital converter ΔΣ Modulators Phase quantizer Quantization noise shaping Jitter shaping Low voltage devices Wireless sensor nodes Bio chips 
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Notes

Acknowledgments

The authors would like to acknowledge useful discussion with Prof. Bahar Jalali-Farahani at Arizona State University, Sleiman Bou-Sleiman at The Ohio State University and Wen-Hung Hsieh at National Chiao Tung University.

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Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringThe Analog VLSI LabColumbusUSA
  2. 2.Department of Electrical and Computer EngineeringThe ElectroScience LabColumbusUSA

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