A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation
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Fully integrated voltage regulators with fast transient response and small area overhead are in high demand for on-chip power management in modern SoCs. A fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90 nm CMOS technology. The LDO also adopts an active frequency compensation scheme that only needs a small amount of compensation capacitors to ensure stability. Simulation results show that, by the synergy of those loops, the LDO improves load regulation accuracy to 3 μV/mA with a 1.2 V input and 1 V output. For a 100 mA load current step with the rise/fall time of 100 ps, the LDO achieves maximum output voltage drop and overshoot of less than 95 mV when loaded by a 600 pF decoupling capacitor and consumes an average bias current of 408 μA. The LDO also features a magnitude notch in both its PSRR and output impedance that provides better suppression upon the spectral components of the supply ripple and the load variation around the notch frequency. Monte Carlo simulations are performed to show that the LDO is robust to process and temperature variations as well as device mismatches. The total area of the LDO excluding the decoupling capacitor is about 0.005 mm2. Performance comparisons with existing solutions indicate significant improvements the proposed LDO achieves.
KeywordsLow-droput regulator (LDO) Output capacitorless Fast transient response Area-efficient
This work was supported in part by the SRC and Texas Analog Center of Excellence under contract 2008-HC-1836.
- 2.Lee, Y.-H., Yang, Y.-Y., Chen, K.-H., Lin, Y.-H., Wang, S.-J., & Zheng, K.-L. et al. (2010). A DVS embedded power management for high efficiency integrated SoC in UWB system. IEEE Journal of Solid-State Circuits, 45(11), 2227–2238.Google Scholar
- 4.Kim, W., Gupta, M. S., Wei, G.-Y., & Brooks, D. (2008). System level analysis of fast, per-core DVFS using on-chip switching regulators. Proceedings of IEEE International Symposium on High Performance Computer Architecture (pp. 123–134).Google Scholar
- 5.Zeng, Z., Ye, X., Feng, Z., & Li, P. (2010). Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation. Proceedings of Design Automation Conference (DAC) (pp. 831–836).Google Scholar
- 9.Gray, P. R., Hurst, P. H., Lewis, S. H., & Meyer, R. G. (2001). AAnalysis and design of analog integrated circuits. New York: Wiley.Google Scholar
- 11.Reddi, V. J., Gupta, M. S., Holloway, G., Wei, G.-Y., Smith, M. D., & Brooks, D. (2009). Voltage emergency prediction: using signatures to reduce opterating margins. Proceedings of IEEE International Symposium High Performance Computer Architecture (pp. 18–29).Google Scholar
- 12.Lam, Y.-H., & Ki, W.-H. (2008). A 0.9 V 0.35 μm adaptively biased CMOS LDO regulator with fast transient response. Proceedings of IEEE International Conference on Solid-State Circuits (ISSCC) (pp. 442–443).Google Scholar
- 14.Jackum, T., Maderbacher, G., Pribyl, W., & Riderer, R. (2011). Fast transient response capacitor-free linear voltage regulator in 65nm CMOS. IEEE International Symposium on Circuits and Systems (ISCAS), 908–905.Google Scholar