Advertisement

A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation

  • Suming LaiEmail author
  • Peng Li
Article

Abstract

Fully integrated voltage regulators with fast transient response and small area overhead are in high demand for on-chip power management in modern SoCs. A fully on-chip low-dropout regulator (LDO) comprised of multiple feedback loops to tackle fast load transients is proposed, designed and simulated in 90 nm CMOS technology. The LDO also adopts an active frequency compensation scheme that only needs a small amount of compensation capacitors to ensure stability. Simulation results show that, by the synergy of those loops, the LDO improves load regulation accuracy to 3 μV/mA with a 1.2 V input and 1 V output. For a 100 mA load current step with the rise/fall time of 100 ps, the LDO achieves maximum output voltage drop and overshoot of less than 95 mV when loaded by a 600 pF decoupling capacitor and consumes an average bias current of 408 μA. The LDO also features a magnitude notch in both its PSRR and output impedance that provides better suppression upon the spectral components of the supply ripple and the load variation around the notch frequency. Monte Carlo simulations are performed to show that the LDO is robust to process and temperature variations as well as device mismatches. The total area of the LDO excluding the decoupling capacitor is about 0.005 mm2. Performance comparisons with existing solutions indicate significant improvements the proposed LDO achieves.

Keywords

Low-droput regulator (LDO) Output capacitorless Fast transient response Area-efficient 

Notes

Acknowledgment

This work was supported in part by the SRC and Texas Analog Center of Excellence under contract 2008-HC-1836.

References

  1. 1.
    Patounakis, G., Li, Y. W., & Shepard, K. L. (2004). A fully integrated on-chip DC–DC conversion and power management system. IEEE Jornal of Solid-State Circuits, 39(3), 443–451.CrossRefGoogle Scholar
  2. 2.
    Lee, Y.-H., Yang, Y.-Y., Chen, K.-H., Lin, Y.-H., Wang, S.-J., & Zheng, K.-L. et al. (2010). A DVS embedded power management for high efficiency integrated SoC in UWB system. IEEE Journal of Solid-State Circuits, 45(11), 2227–2238.Google Scholar
  3. 3.
    Hazucha, P., Karnik, T., Bloechel, B. A., Parsons, C., Finan, D., & Borkar, S. (2005). Area-efficient linear regulator with ultra-fast load regulation. IEEE Journal of Solid-State Circuits, 40(4), 933–940.CrossRefGoogle Scholar
  4. 4.
    Kim, W., Gupta, M. S., Wei, G.-Y., & Brooks, D. (2008). System level analysis of fast, per-core DVFS using on-chip switching regulators. Proceedings of IEEE International Symposium on High Performance Computer Architecture (pp. 123–134).Google Scholar
  5. 5.
    Zeng, Z., Ye, X., Feng, Z., & Li, P. (2010). Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation. Proceedings of Design Automation Conference (DAC) (pp. 831–836).Google Scholar
  6. 6.
    Milliken, R. J., Silva-Martínez, J., & Sánchez Sinencio, E. (2007). Fully on-chip CMOS low-dropout voltage regulator. IEEE Transactions on Circuits and System I: Regular Papers, 54(9), 1879–1890.CrossRefGoogle Scholar
  7. 7.
    Guo, J., & Leung, K. N. (2010). A 6-μW chip-area-efficient output-capacitorless LDO in 90-nm CMOS technology. IEEE Journal of Solid-State Circuits, 45(9), 755–759.MathSciNetCrossRefGoogle Scholar
  8. 8.
    Man, T. Y., Leung, K. N., Leung, C. Y., Mok, P. K. T., & Chan, M. (2008). Development of single-transistor-control LDO based on flipped voltage follower for SoC. IIEEE Transactions on Circuits and System I: Regular Papers, 55(5), 1392–1401.MathSciNetCrossRefGoogle Scholar
  9. 9.
    Gray, P. R., Hurst, P. H., Lewis, S. H., & Meyer, R. G. (2001). AAnalysis and design of analog integrated circuits. New York: Wiley.Google Scholar
  10. 10.
    Or, P. Y., & Leung, K. N. (2010). An output-capacitorless low-dropout regulator with direct voltage-spike detection. IEEE Journal of Solid-State Circuits, 45(2), 458–466.CrossRefGoogle Scholar
  11. 11.
    Reddi, V. J., Gupta, M. S., Holloway, G., Wei, G.-Y., Smith, M. D., & Brooks, D. (2009). Voltage emergency prediction: using signatures to reduce opterating margins. Proceedings of IEEE International Symposium High Performance Computer Architecture (pp. 18–29).Google Scholar
  12. 12.
    Lam, Y.-H., & Ki, W.-H. (2008). A 0.9 V 0.35 μm adaptively biased CMOS LDO regulator with fast transient response. Proceedings of IEEE International Conference on Solid-State Circuits (ISSCC) (pp. 442–443).Google Scholar
  13. 13.
    Ho, E. N. Y., & Mok, P. K. T. (2010). A capacitor-less CMOS active feedback low-dropout regulator with slew-rate enhancement for portable on-chip application. IIEEE Transactions on Circutis and System II: Express Briefs., 57(2), 80–84.CrossRefGoogle Scholar
  14. 14.
    Jackum, T., Maderbacher, G., Pribyl, W., & Riderer, R. (2011). Fast transient response capacitor-free linear voltage regulator in 65nm CMOS. IEEE International Symposium on Circuits and Systems (ISCAS), 908–905.Google Scholar
  15. 15.
    Blakiewicz, G. (2011). Output-capacitorless low-dropout regulator using a cascoded flipped voltage follower. IET Circuits, Devices Systems, 5(5), 418–423.CrossRefGoogle Scholar
  16. 16.
    Alon, E., & Horowitz, M. (2008). Integrated regulation for energy-efficient digital circuits. IEEE Journal of Solid-State Circuits, 43(8), 1795–1807.CrossRefGoogle Scholar
  17. 17.
    El-Nozahi, M., Amer, A., Torres, J., Entesari, K., & Sánchez Sinencio, E. (2010). High PSR low drop-out regulator with feed-forward ripple cancellation technique. IEEE Journal of Solid-State Circuits, 45(3), 565–577.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringTexas A&M UniversityCollege StationUSA

Personalised recommendations