Analog Integrated Circuits and Signal Processing

, Volume 70, Issue 2, pp 241–248 | Cite as

FPGA implementation and testing of a 128 FFT for a MB-OFDM receiver

  • Bruno FernandesEmail author
  • Helena Sarmento


In this paper we discuss the FPGA design of a 128-point Pipelined FFT processor for a multi-band (MB)-OFDM receiver. We implemented two parallel architectures based on the Xilinx Core Generator. The architectures use two or four smaller FFTs in parallel. Results show that time requirements are fulfill when combining Pipelined, Streaming input/output (I/O) architectures with Radix-2 and Radix-4 operations. For Virtex-4, we need four levels of parallelization, but for Virtex-5 only two. Both circuits were synthesized, placed and routed. We tested the circuits on the FPGA, defining test vectors and analyzing outputs signals with Chipscope.





This work has been performed under the project “UWB Receiver: baseband processing using reconfigurable hardware”—PTDC/EEAELC/67993/2006, and was partially supported by FCT (INESC-ID multi-annual funding) through the PIDDAC Program funds."


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© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.INESC-IDLisbonPortugal
  2. 2.INESC-ID/IST/TULisbonPortugal

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