Skip to main content

Advertisement

Log in

Flipped-around multiply-by-two amplifier with unity feedback factor

  • Mixed Signal Letter
  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This letter describes a multiply-by-two amplifier inherently insensitive to capacitor mismatch with an enhanced feedback factor of approximately unity. The proposed flipped-around structure, which operates in a single clock cycle, is based on the series association of two charged capacitors to achieve an accurate gain of two. Due to the series association of the capacitors, a nearly unity feedback factor is achieved, greatly enhancing the energy efficiency of the circuit. Simulations, in a standard 0.13 μm 1.2 V CMOS technology, also show a fourfold linearity improvement over the conventional structure.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4

References

  1. Karanicolas, A. N., Lee, H.-S., & Bacrania, K. L. (1993). A 15-b 1-Msample/s digitally self-calibrated pipeline ADC. IEEE Journal of Solid-State Circuits, 28, 1207–1215.

    Article  Google Scholar 

  2. Li, P. W., Chin, M. J., Gray, P. R., & Castello, R. (1984). A ratio-independent algorithmic analog-to-digital conversion technique. IEEE Journal of Solid-State Circuits, SC-19, 828–836.

    Article  Google Scholar 

  3. Chiu, Y., Gray, P. R., & Nikolic, B. (2004). A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR. IEEE Journal of Solid-State Circuits, 39, 2139–2151.

    Article  Google Scholar 

  4. Song, B., Tompsett, M. F., & Lakshmikumar, K. R. (1988). A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter. IEEE Journal of Solid-State Circuits, 23, 1324–1333.

    Article  Google Scholar 

  5. Quinn, P., & Pribytko, M. (2003). Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 μm CMOS. In Proc. IEEE Custom Integrated Circuits Conference (pp. 425–428).

  6. Goes, J., Pereira, J. C., Paulino, N., & Silva, M. M. (2007). Switched-capacitor multiply-by-two amplifier insensitive to component mismatches. IEEE Transactions on Circuits and Systems II: Express Briefs, 54, 29–33.

    Article  Google Scholar 

  7. Lewis, S. H., Fetterman, H. S., Gross, G. F., Ramachandran, R., & Viswanathan, T. R. (1992). A 10-b 20-Msample/s analog-to-digital converter. IEEE Journal of Solid-State Circuits, 27, 351–358.

    Article  Google Scholar 

Download references

Acknowledgments

This work was supported in part by the Portuguese Foundation for Science and Technology under projects IMPACT (PTDC/EEA-ELC/101421/2008), LEADER (PTDC/EEA-ELC/69791/2006), FCT/CAPES (227/09), and Ph.D. grants BD/41524/2007 and BD/62568/2009.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to M. Figueiredo.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Figueiredo, M., Santin, E., Goes, J. et al. Flipped-around multiply-by-two amplifier with unity feedback factor. Analog Integr Circ Sig Process 68, 133–138 (2011). https://doi.org/10.1007/s10470-011-9642-5

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-011-9642-5

Keywords

Navigation