Advertisement

A one-path subsampling quadrature receiver based on a ΣΔ modulator with distributed resonators

  • E. Prefasi
  • S. Reekmans
  • L. Hernández
  • P. Rombouts
Article
  • 87 Downloads

Abstract

This article presents experimental results of a quadrature bandpass sigma–delta (ΣΔ) modulator based on distributed resonators. The modulator employs transmission lines and transconductors as main components and does not require switches in the loop filter as in the case of switched-capacitor (discrete-time) filters. In addition, the proposed complex modulator does not require a quadrature mixer in the receiver. As main feature, the modulator architecture introduces an innovative way to produce the I and Q outputs that is immune to path mismatch due to the sharing of all the analog circuitry for both paths. The one-bit second-order modulator ADC is able to convert IF signals at fs/2 and 3fs/2 (fs = 50 MHz), achieving an ENOB = 10 bits within a 1 MHz signal bandwidth. Therefore the modulator may be feasible for the typical IF frequencies used in cellular base stations. Furthermore, it provides an image rejection grater than 70 dB. The 0.35 μm BiCMOS chip consumes 28 mW at 3.3 V supply voltage.

Keywords

Analog-to-digital conversion Sigma–delta modulation Quadrature modulator Transmission-line (TL) resonators 

Notes

This work has been sponsored by project TEC2007-67460-C03-03 of the Commission of Science and Technology (CICYT) (Spain) and CCG07-UC3M/TIC-3151 of the CAM (Spain).

References

  1. 1.
    Reekmans, S., Hernandez, L., & Prefasi, E. (2007). A subsampling quadrature sigma delta modulator based on distributed resonators for use in radio receiver. IEEE Transactions on Circuits and Systems II: Express Briefs, 54(9), 820–824.CrossRefGoogle Scholar
  2. 2.
    Prefasi, E., Hernandez, L., Reekmans, S., & Rombouts, P. (2009). Design and implementation of a band-pass sigma delta modulator with distributed resonators. Analog Integrated Circuits and Signal Processing, 58(9), 243–253.CrossRefGoogle Scholar
  3. 3.
    Schreier, R., & Snelgrove, M. (1989). Bandpass sigma–delta modulation. Electronic Letters, 25, 1560–1561.CrossRefGoogle Scholar
  4. 4.
    Steyaert M. et al. (2002). A fully-integrated GPS receiver front-end with 40mW power consumption. In Proc. IEEE Int. Solid-State Circuits Conf., San Francisco, CA (pp. 396–397), Feb 2002.Google Scholar
  5. 5.
    Henkel, F., et al. (2002). A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma–delta modulator for low-IF radio receivers. IEEE Journal of Solid-State Circuits, 37(12), 1628–1635.CrossRefGoogle Scholar
  6. 6.
    Arias, J., et al. (2006). A 32-mW 320-MHz continuous-time complex delta–sigma ADC for multi-mode wireless-LAN receivers. IEEE Journal of Solid-State Circuits, 41(2), 339–351.CrossRefGoogle Scholar
  7. 7.
    Schreier, R., et al. (2006). A 375-mw quadrature bandpass delta sigma ADC with 8.5-MHz BW and 90-dB DR at 44 MHz. IEEE Journal of Solid-State Circuits, 41(12), 2632–2640.CrossRefGoogle Scholar
  8. 8.
    Hernandez L., Rombouts P., & Prefasi E. (2004). A jitter insensitive continuous-time sigma delta modulator using transmission lines. In IEEE Int. Conf. on Electronics, Circuits and Systems, ICECS 2004, Tel-Aviv, Israel (pp. 109–112). Dec 2004.Google Scholar
  9. 9.
    Hernandez, L., Prefasi, E., & Rombouts, P. (2006) A continuous-time band-pass sigma delta modulator implemented in 0.35u BiCMOS using transmission lines. In IEEE Proceedings Int. Symp. on Circuits and Systems, ISCAS 2006, Island of Kos, Greece, May 2006.Google Scholar
  10. 10.
    Kaplan, T. S., & Jensen, J. F. (2005). Continuous-time ΔΣ modulators using distributed resonators. IEEE Transactions on Circuits and Systems I, 52(11), 2397–2403.CrossRefGoogle Scholar
  11. 11.
    Valkama, M., & Renfors, M. (2004). A novel image rejection architecture for quadrature radio receivers. IEEE Transactions on Circuits and Systems II: Express Briefs, 51(2), 61–68.CrossRefGoogle Scholar
  12. 12.
    Chang, Z.-Y., et al. (1995). A CMOS analog front-end circuit for an FDM-based ADSL system. IEEE Journal of Solid-State Circuits, 30, 1449–1456.CrossRefGoogle Scholar
  13. 13.
    Luh, L., Choma, J., Jr, & Draper, J. (2000). A continuous-time common-mode feedback circuit (CMFB) for high-impedance current-mode applications. IEEE Transactions on Circuits and Systems II: Express Briefs, 47(4), 363–369.CrossRefGoogle Scholar
  14. 14.
    Geerts, Y., Marques, A. M., Steyaert, M. S. J., & Sansen, W. (1999). A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications. IEEE Journal of Solid-State Circuits, 34(7), 927–936.CrossRefGoogle Scholar
  15. 15.
    Van den Bosch, A., Borremans, M. A. F., Steyaert, M. S. J., & Sansen, W. (2001). 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter. IEEE Journal of Solid-State Circuits, 36(3), 315–324.CrossRefGoogle Scholar
  16. 16.
    Hernandez L., & Prefasi E. (2008). A subsampling bandpass SD modulator with lumped and distributed resonators. In Proc. IEEE Int. Symp. Circuits Syst., Seattle, WA, May 2008.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • E. Prefasi
    • 1
  • S. Reekmans
    • 2
  • L. Hernández
    • 1
  • P. Rombouts
    • 2
  1. 1.Department of Electronics TechnologyCarlos III UniversityMadridSpain
  2. 2.Ghent UniversityGhentBelgium

Personalised recommendations