Advertisement

Analog Integrated Circuits and Signal Processing

, Volume 64, Issue 3, pp 271–280 | Cite as

Jitter characteristics of an on-chip voltage reference-locked time-to-digital converter

  • Ilkka NissinenEmail author
  • Juha Kostamovaara
Article
  • 168 Downloads

Abstract

The noise and jitter characteristics of an on-chip voltage reference-locked ring oscillator used in the time-to-digital converter (TDC) of the integrated receiver of a pulsed time-of-flight laser rangefinder are presented. The frequency of the ring oscillator, 683 MHz, was locked to the on-chip voltage reference by means of a frequency-to-voltage converter, resulting in better than 90 ppm/°C stability. The noise and jitter transfer characteristics of the loop were derived, and simulations were performed to see the effects of different noise types (white and 1/f noise) on the cumulative jitter of the locked ring oscillator. Finally, these results were verified by jitter measurements performed using an integrated time-to-digital converter (TDC) fabricated on the same die (0.18 μm CMOS process). The cumulative jitter of the on-chip reference-locked ring oscillator was less than 30 ps (sigma value) over a time range of 70 ns, which made it possible to use this oscillator as the heart of a TDC when aiming at centimetre-level precision (1 cm = 67 ps) in laser ranging.

Keywords

Jitter Reference locked oscillator Time-to-digital converter Phase noise 

Notes

Acknowledgments

This work was supported financially by the Finnish Funding Agency for Technology and Innovation (TEKES), the Academy of Finland and certain industrial companies, all of which are gratefully acknowledged.

References

  1. 1.
    Nissinen, I., & Kostamovaara, J. (2009). On-chip voltage reference-based time-to-digital converter for pulsed time-of-flight laser radar measurements. IEEE Transaction on Instrumentation and Measurements, 58(6), 1938–1948.CrossRefGoogle Scholar
  2. 2.
    Staszewski, R. B., et al. (2004). All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS. IEEE Journal of Solid-State Circuits, 39, 2278–2291.CrossRefGoogle Scholar
  3. 3.
    Nelson, B., & Soma, M. (2004). On-chip calibration technique for delay line based BIST jitter measurement. In Proceedings of international symposium on circuits and systems (ISCAS’04), Vancouver, Canada, Vol. 1, pp. 944–947.Google Scholar
  4. 4.
    Djemouai, A., Sawan, M., & Slamani, M. (1999). New circuit techniques based on a high performance frequency-to-voltage converter. In Proceedings of IEEE international conference on electronics, circuits and systems (ICECS’99), Montreal, Canada, Vol. 1, pp. 13–16.Google Scholar
  5. 5.
    Djemouai, A., Sawan, M., & Slamani, M. (1998). High performance integrated CMOS frequency-to-voltage converter. In Proceedings of international conference on microelectronics (ICM’98), Monastir, Tunisia, pp. 63–66.Google Scholar
  6. 6.
    Chen, J., & Shi, B. (2003). 1 V CMOS current reference with 50 ppm/°C temperature coefficient. Electronics Letters, 39, 2.CrossRefGoogle Scholar
  7. 7.
    Nissinen, I., & Kostamovaara, J. (2004). A low voltage CMOS constant current–voltage reference circuit. In Proceedings of international symposium on circuits and systems (ISCAS’04), Vancouver, Canada, Vol. 1, pp. 381–384.Google Scholar
  8. 8.
    Nissinen, I., & Kostamovaara, J. (2008). Noise and jitter transfer characteristics of an on-chip voltage reference-locked loop. In Proceedings of 26th IEEE NORCHIP conference, Tallinn, Estonia, pp. 212–216.Google Scholar
  9. 9.
    Hajimiri, A., & Lee, T. H. (2001). The design of low noise oscillators. USA: Kluwer. 4th Printing.Google Scholar
  10. 10.
    Leeson, D. B. (1966). A simple model of feedback oscillator noise spectrum. Proceedings of the IEEE, 54(2), 329.CrossRefGoogle Scholar
  11. 11.
    Mantyniemi, A., Rahkonen, T., & Kostamovaara, J. (2009). A CMOS time-to-digital converter (TDC) based on a cyclic time domain successive approximation interpolation method. IEEE Journal of Solid-State Circuits, 44(11), 3067–3078.CrossRefGoogle Scholar
  12. 12.
    Mota, M., et. al. (2000). A flexiple multi-channel high-resolution time-to-digital converter ASIC. In Proceedings of nuclear science symposium conference record, Lyon, France, Vol. 2, pp. 155–159.Google Scholar
  13. 13.
    Chen, P., et al. (2007). A PVT insensitive vernier-based time-to-digital converter with extended input range and high accuracy. IEEE Transaction on Nuclear Science, 54(2), 294–302.CrossRefGoogle Scholar
  14. 14.
    Tisa, S., et al. (2003). Monolithic time-to-digital converter with 20 ps resolution. In Proceedings of European solid-state circuit conference (ESSCIRC’03), Estoril, Portugal, pp. 465–468.Google Scholar
  15. 15.
    Chen, C., et al. (2005). A precise cyclic CMOS time-to-digital converter with low thermal sensitivity. IEEE Transaction on Nuclear Science, 52(4), 834–838.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Department of Electrical and Information Engineering, Electronics LaboratoryUniversity of OuluOuluFinland

Personalised recommendations