Analog Integrated Circuits and Signal Processing

, Volume 65, Issue 3, pp 389–398 | Cite as

A high speed programmable focal-plane SIMD vision chip

  • Dominique Ginhac
  • Jérôme Dubois
  • Barthélémy Heyrman
  • Michel Paindavoine


A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Each pixel include a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64 × 64 pixel proof-of-concept chip was fabricated in a 0.35 μm standard CMOS process, with a pixel size of 35 μm × 35 μm. The chip can capture raw images up to 10,000 fps and runs low-level image processing at a framerate of 2,000–5,000 fps.


CMOS image sensor Parallel architecture SIMD High-speed image processing Analog arithmetic unit 


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Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • Dominique Ginhac
    • 1
  • Jérôme Dubois
    • 1
  • Barthélémy Heyrman
    • 1
  • Michel Paindavoine
    • 1
  1. 1.LE2I—Université de BourgogneDijon CedexFrance

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